9 #define LPSS_CLOCK_CTL_REG 0x200
10 #define LPSS_CNT_CLOCK_EN 1
11 #define LPSS_CNT_CLK_UPDATE (1 << 31)
12 #define LPSS_CLOCK_DIV_N(n) (((n) & 0x7fff) << 16)
13 #define LPSS_CLOCK_DIV_M(m) (((m) & 0x7fff) << 1)
16 #define LPSS_RESET_CTL_REG 0x204
26 #define LPSS_CNT_RST_RELEASE 3
29 #define LPSS_DMA_RST_RELEASE (1 << 2)
32 #define PME_CTRL_STATUS 0x84
34 #define POWER_STATE_MASK 3
41 if (
val == 0xFFFFFFFF)
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
#define LPSS_CNT_CLK_UPDATE
#define LPSS_CNT_CLOCK_EN
void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state)
void lpss_reset_release(uintptr_t base)
#define LPSS_CLOCK_DIV_M(m)
bool lpss_is_controller_in_reset(uintptr_t base)
#define LPSS_CNT_RST_RELEASE
void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
#define LPSS_CLOCK_CTL_REG
#define LPSS_CLOCK_DIV_N(n)
#define LPSS_RESET_CTL_REG
static __always_inline uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg)
static __always_inline void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)