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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <fsp/soc_binding.h>
#include <commonlib/helpers.h>
#include <soc/bootblock.h>
#include <soc/gpio_defs.h>
#include <soc/uart.h>
Go to the source code of this file.
Macros | |
#define | ELEM_OF_UART_TAB ARRAY_SIZE(legacy_uart_ioadr_tab) |
Functions | |
static void | pci_early_hsuart_device_probe (u8 bus, u8 dev, u8 func, u32 mmio_base) |
static void | early_config_gpio (void) |
void | early_uart_init (void) |
Variables | |
static uint16_t | legacy_uart_ioadr_tab [] = {0x3F8, 0x2F8, 0x3E8, 0x2E8} |
#define ELEM_OF_UART_TAB ARRAY_SIZE(legacy_uart_ioadr_tab) |
Definition at line 56 of file uart.c.
References B_PCH_GPIO_PAD_MODE, N_PCH_GPIO_PAD_MODE, PCH_PCR_ADDRESS, PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N, R_PAD_CFG_DW0_SATA0_SDOUT, R_PAD_CFG_DW0_SATA1_SDOUT, R_PAD_CFG_DW0_SMB3_CLTT_CLK, R_PAD_CFG_DW0_UART0_RXD, R_PAD_CFG_DW0_UART0_TXD, R_PAD_CFG_DW0_UART1_RXD, R_PAD_CFG_DW0_UART1_TXD, read32(), V_PCH_GPIO_PAD_MODE_NAT_1, V_PCH_GPIO_PAD_MODE_NAT_2, V_PCH_GPIO_PAD_MODE_NAT_3, and write32().
Referenced by early_uart_init().
Definition at line 161 of file uart.c.
References BUILD_BUG_ON, DENVERTON_UARTS_TO_INI, early_config_gpio(), ELEM_OF_UART_TAB, legacy_uart_ioadr_tab, and pci_early_hsuart_device_probe().
Referenced by bootblock_soc_early_init().
Definition at line 17 of file uart.c.
References CONFIG, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, PCI_DEV, pci_read_config16(), pci_write_config16(), pci_write_config32(), PSR_OFFSET, and SIZE_OF_HSUART_RES.
Referenced by early_uart_init().
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static |
Definition at line 13 of file uart.c.
Referenced by early_uart_init().