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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Functions | |
void | apollolake_init_cpus (struct device *dev) |
void | mainboard_devtree_update (struct device *dev) |
static void | flush_l1d_to_l2 (void) |
Definition at line 263 of file cpu.c.
References CONFIG, fast_spi_cache_bios_region(), device::link_list, and soc_init_cpus().
Definition at line 15 of file cpu.h.
References FLUSH_DL1_L2, msr_struct::lo, MSR_POWER_MISC, rdmsr(), and wrmsr().
Referenced by platform_segment_loaded().
Definition at line 230 of file mainboard.c.
References audio_codec_device_update(), babymega_i2c_speed_config, babytiger_i2c_speed_config, device::chip_info, soc_intel_apollolake_config::common_soc_config, soc_intel_common_config::i2c, rabbid_i2c_speed_config, SKU_0_ASTRONAUT, SKU_10_LAVA, SKU_1_ASTRONAUT, SKU_28_RABBID_RUGGED, SKU_2_SANTA, SKU_30_BABYTIGER, SKU_31_RABBID, SKU_32_RABBID, SKU_33_BABYTIGER, SKU_3_SANTA, SKU_4_LAVA, SKU_52_BABYMEGA, SKU_53_BABYMEGA, SKU_5_LAVA, SKU_61_ASTRONAUT, SKU_62_ASTRONAUT, SKU_9_LAVA, SKU_ALAN, SKU_BIGDADDY, SKU_BIGDADDY_KBDBKLIGHT, sku_id(), dw_i2c_bus_config::speed_config, usb2_eye_per_port::Usb20IUsbTxEmphasisEn, usb2_eye_per_port::Usb20PerPortPeTxiSet, usb2_eye_per_port::Usb20PerPortTxiSet, usb2_eye_per_port::Usb20PerPortTxPeHalf, soc_intel_apollolake_config::usb2eye, variant_board_sku(), variant_update_devtree(), and wifi_device_update().
Referenced by mainboard_init(), and platform_fsp_silicon_init_params_cb().