coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c File Reference
#include <acpi/acpi_device.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <soc/gpio_soc_defs.h>
#include <soc/pci_devs.h>
#include <soc/soc_chip.h>
#include <string.h>
#include <drivers/intel/dptf/chip.h>
#include "board_id.h"
#include <intelblocks/power_limit.h>
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Go to the source code of this file.

Data Structures

struct  board_id_iom_port_config
 

Functions

 WEAK_DEV_PTR (dptf_policy)
 
void variant_update_power_limits (void)
 
static void variant_update_typec_init_config (void)
 
void variant_devtree_update (void)
 

Variables

const struct cpu_power_limits limits []
 
static const struct typec_aux_bias_pads pad_config = { GPP_E23, GPP_E22 }
 
static const struct board_id_iom_port_config port_config []
 

Function Documentation

◆ variant_devtree_update()

void variant_devtree_update ( void  )

Definition at line 93 of file ramstage.c.

References variant_update_power_limits(), and variant_update_typec_init_config().

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◆ variant_update_power_limits()

void variant_update_power_limits ( void  )

Definition at line 27 of file ramstage.c.

◆ variant_update_typec_init_config()

static void variant_update_typec_init_config ( void  )
static

Definition at line 76 of file ramstage.c.

References ARRAY_SIZE, board_id(), config, CONFIG, config_of_soc, get_board_id(), memcpy(), board_id_iom_port_config::port, and port_config.

Referenced by variant_devtree_update().

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◆ WEAK_DEV_PTR()

WEAK_DEV_PTR ( dptf_policy  )

Variable Documentation

◆ limits

const struct cpu_power_limits limits[]
Initial value:
= {
{ PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000, 123000 },
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000, 123000 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 },
}
#define PCI_DID_INTEL_ADL_P_ID_7
Definition: pci_ids.h:4069
#define PCI_DID_INTEL_ADL_P_ID_3
Definition: pci_ids.h:4065
#define PCI_DID_INTEL_ADL_P_ID_5
Definition: pci_ids.h:4067
#define PCI_DID_INTEL_ADL_P_ID_6
Definition: pci_ids.h:4068

Definition at line 1 of file ramstage.c.

◆ pad_config

const struct typec_aux_bias_pads pad_config = { GPP_E23, GPP_E22 }
static

Definition at line 27 of file ramstage.c.

◆ port_config

const struct board_id_iom_port_config port_config[]
static
Initial value:
= {
}
@ TYPE_C_PORT_2
Definition: tcss.h:75
@ TYPE_C_PORT_1
Definition: tcss.h:74
@ TYPE_C_PORT_0
Definition: tcss.h:73
@ ADL_M_LP4
Definition: variants.h:24
@ ADL_P_LP4_1
Definition: variants.h:12
@ ADL_P_LP4_2
Definition: variants.h:13
@ ADL_P_LP5_1
Definition: variants.h:18
@ ADL_P_DDR4_2
Definition: variants.h:22
@ ADL_M_LP5
Definition: variants.h:25
@ ADL_P_DDR4_1
Definition: variants.h:21
@ ADL_P_LP5_2
Definition: variants.h:19

Referenced by variant_update_typec_init_config().