coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <device/mmio.h>
#include <delay.h>
#include <soc/emi.h>
#include <soc/dramc_pi_api.h>
#include <soc/dramc_param.h>
#include <soc/dramc_register.h>
#include <soc/infracfg.h>
#include <string.h>
#include <timer.h>
Go to the source code of this file.
Data Structures | |
struct | ac_time |
Variables | |
static const struct ac_time | ac_timing_tbl [LP4X_DDRFREQ_MAX] |
static const struct ac_time | ac_timing_cbt_tbl [LP4X_DDRFREQ_MAX] |
Definition at line 858 of file dramc_init_setting.c.
References ch, CHANNEL_A, CHANNEL_B, CHANNEL_MAX, CKE_FIXOFF, DRAMC_BROADCAST_OFF, dramc_cke_fix_onoff(), dramc_get_broadcast(), dramc_set_broadcast(), setbits32, and udelay().
Definition at line 63 of file dramc_init_setting.c.
References addr, ARRAY_SIZE, ch, CHANNEL_A, CHANNEL_B, CKE_DYNAMIC, clrbits32, clrsetbits32, die(), DLL_MASTER, DLL_SLAVE, dramc_cke_fix_onoff(), LP4X_DDR1600, LP4X_DDR2400, LP4X_DDR3200, LP4X_DDR3600, read32(), SET32_BITFIELDS, setbits32, udelay(), value, and write32().
Definition at line 556 of file dramc_init_setting.c.
References ch, CHANNEL_MAX, clrsetbits32, FSP_0, get_freq_fsq(), and LP4X_DDR1600.
Definition at line 1862 of file dramc_init_setting.c.
References ac_timing_cbt_tbl, ac_timing_tbl, ch, CHANNEL_MAX, ac_time::ckelckcnt, ac_time::ckeprd, clrsetbits32, ac_time::datlat, ac_time::dqsinctl, LP4X_DDR1600, LP4X_DDR3600, memcpy(), ODT_ON, ac_time::r_dmcatrain_intv, ac_time::r_dmfspchg_prdcnt, ac_time::r_dmmrw_intv, read32(), ac_time::refcnt, ac_time::refcnt_fr_clk, ac_time::tfaw, ac_time::tfaw_05T, ac_time::tmrr2w_odt_on, ac_time::tras, ac_time::tras_05T, ac_time::trc, ac_time::trc_05T, ac_time::trcd, ac_time::trcd_05T, ac_time::trfc, ac_time::trfc_05T, ac_time::trfcpb, ac_time::trfcpb_05T, ac_time::trp, ac_time::trp_05T, ac_time::trpab, ac_time::trpab_05T, ac_time::trrd, ac_time::trrd_05T, ac_time::trtp, ac_time::trtp_05T, ac_time::trtpd, ac_time::trtpd_05T, ac_time::trtw_odt_on, ac_time::trtw_odt_on_05T, ac_time::twr, ac_time::twr_05T, ac_time::twtpd, ac_time::twtpd_05T, ac_time::twtr, ac_time::twtr_05T, ac_time::txp, ac_time::txp_05T, ac_time::txrefcnt, ac_time::tzqcs, ac_time::xrtr2r, ac_time::xrtr2w, ac_time::xrtw2r, ac_time::xrtw2w, and ac_time::zqlat2.
Referenced by dramc_init().
Definition at line 14 of file dramc_init_setting.c.
References ch, CKE_DYNAMIC, and SET32_BITFIELDS.
Referenced by auto_refresh_cke_off(), cbt_entry(), cbt_exit(), ddr_phy_pll_setting(), dqsosc_auto(), dramc_apply_config_after_calibration(), dramc_mode_reg_write(), dramc_power_on_sequence(), and dramc_zq_calibration().
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Definition at line 632 of file dramc_init_setting.c.
References CHANNEL_A, CHANNEL_B, CHANNEL_MAX, die(), DQS_NUMBER, dramc_dbg, dramc_duty_set_clk_delay(), dramc_duty_set_dqs_delay(), DRAMC_PARAM_SOURCE_FLASH, DRAMC_PARAM_SOURCE_SDRAM_CONFIG, LP4X_DDR1600, LP4X_DDR2400, LP4X_DDR3200, LP4X_DDR3600, and params.
Referenced by dramc_init().
Definition at line 592 of file dramc_init_setting.c.
References ch, clrsetbits32, and RANK_MAX.
Referenced by dramc_duty_calibration().
Definition at line 611 of file dramc_init_setting.c.
References ch, clrsetbits32, DQS_NUMBER, and RANK_MAX.
Referenced by dramc_duty_calibration().
Definition at line 313 of file dramc_init_setting.c.
References ch, clrbits32, clrsetbits32, setbits32, and udelay().
Referenced by update_initial_settings().
void dramc_init | ( | const struct sdram_params * | params, |
u8 | freq_group, | ||
struct dram_shared_data * | shared | ||
) |
Definition at line 1974 of file dramc_init_setting.c.
References ddr_update_ac_timing(), dramc_duty_calibration(), dramc_mode_reg_init(), dramc_setting(), dvfs_settings(), dram_shared_data::impedance, dram_shared_data::mr, and params.
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Definition at line 738 of file dramc_init_setting.c.
References CBT_R0_NORMAL_R1_BYTE, ch, CHANNEL_MAX, clrsetbits32, DRAMC_BROADCAST_OFF, dramc_dbg, dramc_get_broadcast(), dramc_mode_reg_write(), dramc_power_on_sequence(), dramc_set_broadcast(), dramc_zq_calibration(), FSP_0, FSP_1, FSP_MAX, get_freq_fsq(), LP4X_DDR1600, LP4X_DDR2400, LP4X_DDR3200, LP4X_DDR3600, mr_value::MR01Value, mr_value::MR13Value, params, RANK_0, and RANK_MAX.
Referenced by dramc_init().
Definition at line 535 of file dramc_init_setting.c.
References ch, CHANNEL_A, CHANNEL_B, CHANNEL_MAX, CKE_FIXOFF, CKE_FIXON, clrbits32, dramc_cke_fix_onoff(), setbits32, and udelay().
Referenced by dramc_mode_reg_init().
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Definition at line 1031 of file dramc_init_setting.c.
Referenced by dramc_init().
Definition at line 873 of file dramc_init_setting.c.
References _SELPH_DQS_BITS, ch, clrbits32, clrsetbits32, SELPH_DQS0_1600, SELPH_DQS1_1600, and value.
Definition at line 950 of file dramc_init_setting.c.
References _SELPH_DQS_BITS, ch, clrsetbits32, SELPH_DQS0_2400, SELPH_DQS1_2400, setbits32, and value.
Definition at line 1025 of file dramc_init_setting.c.
References ch, clrsetbits32, SELPH_DQS0_3600, and SELPH_DQS1_3600.
Definition at line 695 of file dramc_init_setting.c.
References addr, ARRAY_SIZE, ch, CKE_FIXON, dramc_cke_fix_onoff(), dramc_dbg, read32(), SET32_BITFIELDS, setbits32, TIMEOUT_US, udelay(), value, wait_us, and write32().
Referenced by dramc_mode_reg_init().
Definition at line 29 of file dramc_init_setting.c.
References ch, CHANNEL_MAX, clrsetbits32, die(), LP4X_DDR1600, LP4X_DDR2400, LP4X_DDR3200, LP4X_DDR3600, and setbits32.
Referenced by dramc_init().
Definition at line 337 of file dramc_init_setting.c.
References ch, CHANNEL_MAX, clrbits32, clrsetbits32, DRAMC_BROADCAST_OFF, DRAMC_BROADCAST_ON, dramc_gating_mode(), dramc_set_broadcast(), FSP_1, get_freq_fsq(), SET32_BITFIELDS, and setbits32.
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Definition at line 1031 of file dramc_init_setting.c.
Referenced by ddr_update_ac_timing().
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Definition at line 1031 of file dramc_init_setting.c.
Referenced by ddr_update_ac_timing().