Go to the source code of this file.
◆ MAX77620_AME_GPIO
#define MAX77620_AME_GPIO 0x40 |
◆ MAX77620_CID0_REG
#define MAX77620_CID0_REG 0x58 |
◆ MAX77620_CID1_REG
#define MAX77620_CID1_REG 0x59 |
◆ MAX77620_CID2_REG
#define MAX77620_CID2_REG 0x5A |
◆ MAX77620_CID3_REG
#define MAX77620_CID3_REG 0x5B |
◆ MAX77620_CID4_REG
#define MAX77620_CID4_REG 0x5C |
◆ MAX77620_CID5_REG
#define MAX77620_CID5_REG 0x5D |
◆ MAX77620_CNFG1_L0_REG
#define MAX77620_CNFG1_L0_REG 0x23 |
◆ MAX77620_CNFG1_L1_REG
#define MAX77620_CNFG1_L1_REG 0x25 |
◆ MAX77620_CNFG1_L2_REG
#define MAX77620_CNFG1_L2_REG 0x27 |
◆ MAX77620_CNFG1_L3_REG
#define MAX77620_CNFG1_L3_REG 0x29 |
◆ MAX77620_CNFG1_L4_REG
#define MAX77620_CNFG1_L4_REG 0x2B |
◆ MAX77620_CNFG1_L5_REG
#define MAX77620_CNFG1_L5_REG 0x2D |
◆ MAX77620_CNFG1_L6_REG
#define MAX77620_CNFG1_L6_REG 0x2F |
◆ MAX77620_CNFG1_L7_REG
#define MAX77620_CNFG1_L7_REG 0x31 |
◆ MAX77620_CNFG1_L8_REG
#define MAX77620_CNFG1_L8_REG 0x33 |
◆ MAX77620_CNFG2_L0_REG
#define MAX77620_CNFG2_L0_REG 0x24 |
◆ MAX77620_CNFG2_L1_REG
#define MAX77620_CNFG2_L1_REG 0x26 |
◆ MAX77620_CNFG2_L2_REG
#define MAX77620_CNFG2_L2_REG 0x28 |
◆ MAX77620_CNFG2_L3_REG
#define MAX77620_CNFG2_L3_REG 0x2A |
◆ MAX77620_CNFG2_L4_REG
#define MAX77620_CNFG2_L4_REG 0x2C |
◆ MAX77620_CNFG2_L5_REG
#define MAX77620_CNFG2_L5_REG 0x2E |
◆ MAX77620_CNFG2_L6_REG
#define MAX77620_CNFG2_L6_REG 0x30 |
◆ MAX77620_CNFG2_L7_REG
#define MAX77620_CNFG2_L7_REG 0x32 |
◆ MAX77620_CNFG2_L8_REG
#define MAX77620_CNFG2_L8_REG 0x34 |
◆ MAX77620_CNFG2SD_REG
#define MAX77620_CNFG2SD_REG 0x22 |
◆ MAX77620_CNFG3_LDO_REG
#define MAX77620_CNFG3_LDO_REG 0x35 |
◆ MAX77620_GPIO0_REG
#define MAX77620_GPIO0_REG 0x36 |
◆ MAX77620_GPIO1_REG
#define MAX77620_GPIO1_REG 0x37 |
◆ MAX77620_GPIO2_REG
#define MAX77620_GPIO2_REG 0x38 |
◆ MAX77620_GPIO3_REG
#define MAX77620_GPIO3_REG 0x39 |
◆ MAX77620_GPIO4_REG
#define MAX77620_GPIO4_REG 0x3A |
◆ MAX77620_GPIO5_REG
#define MAX77620_GPIO5_REG 0x3B |
◆ MAX77620_GPIO6_REG
#define MAX77620_GPIO6_REG 0x3C |
◆ MAX77620_GPIO7_REG
#define MAX77620_GPIO7_REG 0x3D |
◆ MAX77620_GPIO_PDE_GPIO
#define MAX77620_GPIO_PDE_GPIO 0x3F |
◆ MAX77620_GPIO_PUE_GPIO
#define MAX77620_GPIO_PUE_GPIO 0x3E |
◆ MAX77620_REG_ONOFF_CFG1
#define MAX77620_REG_ONOFF_CFG1 0x41 |
◆ MAX77620_REG_ONOFF_CFG2
#define MAX77620_REG_ONOFF_CFG2 0x42 |
◆ MAX77620_SD0_REG
#define MAX77620_SD0_REG 0x16 |
Definition at line 8 of file pmic.h.
◆ MAX77620_SD1_REG
#define MAX77620_SD1_REG 0x17 |
Definition at line 9 of file pmic.h.
◆ MAX77620_SD2_REG
#define MAX77620_SD2_REG 0x18 |
◆ MAX77620_SD3_REG
#define MAX77620_SD3_REG 0x19 |
◆ MAX77620_VDVSSD0_REG
#define MAX77620_VDVSSD0_REG 0x1B |
◆ MAX77621_CONTROL1_REG
#define MAX77621_CONTROL1_REG 0x02 |
◆ MAX77621_CONTROL2_REG
#define MAX77621_CONTROL2_REG 0x03 |
◆ MAX77621_VOUT_DVC_REG
#define MAX77621_VOUT_DVC_REG 0x01 |
◆ MAX77621_VOUT_REG
#define MAX77621_VOUT_REG 0x00 |
◆ pmic_init()
Definition at line 34 of file pmic.c.
References BIOS_DEBUG, board_id(), MAX77620_AME_GPIO, MAX77620_CNFG1_L1_REG, MAX77620_CNFG1_L2_REG, MAX77620_CNFG2SD_REG, MAX77620_GPIO1_REG, MAX77620_GPIO5_REG, MAX77620_SD0_REG, MAX77620_SD1_REG, MAX77620_VDVSSD0_REG, MAX77621_CONTROL1_REG, MAX77621_CONTROL2_REG, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_REG, pmic_slam_defaults(), pmic_write_reg(), pmic_write_reg_77620(), pmic_write_reg_77621(), printk, and udelay().
Referenced by bootblock_mainboard_init().
◆ pmic_write_reg_77620()