#include <device/mmio.h>
#include <soc/cdp.h>

Include dependency graph for iomap.h:

Macros
#define	readl_i(a) read32((const void *)(a))

#define	writel_i(v, a) write32((void *)a, v)

#define	clrsetbits32_i(addr, clear, set) clrsetbits32(((void *)(addr)), (clear), (set))

#define	MSM_CLK_CTL_BASE ((void *)0x00900000)

#define	MSM_TMR_BASE ((void *)0x0200A000)

#define	MSM_GPT_BASE (MSM_TMR_BASE + 0x04)

#define	MSM_DGT_BASE (MSM_TMR_BASE + 0x24)

#define	GPT_REG(off) (MSM_GPT_BASE + (off))

#define	DGT_REG(off) (MSM_DGT_BASE + (off))

#define	APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)

#define	APCS_WDT0_RST (MSM_TMR_BASE + 0x0038)

#define	APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C)

#define	APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C)

#define	APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820)

#define	GPT_MATCH_VAL GPT_REG(0x0000)

#define	GPT_COUNT_VAL GPT_REG(0x0004)

#define	GPT_ENABLE GPT_REG(0x0008)

#define	GPT_CLEAR GPT_REG(0x000C)

#define	GPT1_MATCH_VAL GPT_REG(0x00010)

#define	GPT1_COUNT_VAL GPT_REG(0x00014)

#define	GPT1_ENABLE GPT_REG(0x00018)

#define	GPT1_CLEAR GPT_REG(0x0001C)

#define	DGT_MATCH_VAL DGT_REG(0x0000)

#define	DGT_COUNT_VAL DGT_REG(0x0004)

#define	DGT_ENABLE DGT_REG(0x0008)

#define	DGT_CLEAR DGT_REG(0x000C)

#define	DGT_CLK_CTL DGT_REG(0x0010)

#define	RPM_INT ((void *)0x63020)

#define	RPM_INT_ACK ((void *)0x63060)

#define	RPM_SIGNAL_COOKIE ((void *)0x47C20)

#define	RPM_SIGNAL_ENTRY ((void *)0x47C24)

#define	RPM_FW_MAGIC_NUM 0x4D505242

#define	TLMM_BASE_ADDR ((void *)0x00800000)

#define	GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)

#define	GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4)

#define	USB_HOST2_XHCI_BASE 0x10000000

#define	USB_HOST2_DWC3_BASE 0x1000C100

#define	USB_HOST2_PHY_BASE 0x100F8800

#define	USB_HOST1_XHCI_BASE 0x11000000

#define	USB_HOST1_DWC3_BASE 0x1100C100

#define	USB_HOST1_PHY_BASE 0x110F8800

#define	GSBI_4 4

#define	UART1_DM_BASE 0x12450000

#define	UART_GSBI1_BASE 0x12440000

#define	UART2_DM_BASE 0x12490000

#define	UART_GSBI2_BASE 0x12480000

#define	UART4_DM_BASE 0x16340000

#define	UART_GSBI4_BASE 0x16300000

#define	UART2_DM_BASE 0x12490000

#define	UART_GSBI2_BASE 0x12480000

#define	GSBI1_BASE ((void *)0x12440000)

#define	GSBI2_BASE ((void *)0x12480000)

#define	GSBI3_BASE ((void *)0x16200000)

#define	GSBI4_BASE ((void *)0x16300000)

#define	GSBI5_BASE ((void *)0x1A200000)

#define	GSBI6_BASE ((void *)0x16500000)

#define	GSBI7_BASE ((void *)0x16600000)

#define	GSBI1_CTL_REG (GSBI1_BASE + (0x0))

#define	GSBI2_CTL_REG (GSBI2_BASE + (0x0))

#define	GSBI3_CTL_REG (GSBI3_BASE + (0x0))

#define	GSBI4_CTL_REG (GSBI4_BASE + (0x0))

#define	GSBI5_CTL_REG (GSBI5_BASE + (0x0))

#define	GSBI6_CTL_REG (GSBI6_BASE + (0x0))

#define	GSBI7_CTL_REG (GSBI7_BASE + (0x0))

#define	GSBI_QUP1_BASE (GSBI1_BASE + 0x20000)

#define	GSBI_QUP2_BASE (GSBI2_BASE + 0x20000)

#define	GSBI_QUP3_BASE (GSBI3_BASE + 0x80000)

#define	GSBI_QUP4_BASE (GSBI4_BASE + 0x80000)

#define	GSBI_QUP5_BASE (GSBI5_BASE + 0x80000)

#define	GSBI_QUP6_BASE (GSBI6_BASE + 0x80000)

#define	GSBI_QUP7_BASE (GSBI7_BASE + 0x80000)

#define	GSBI_CTL_PROTO_I2C 2

#define	GSBI_CTL_PROTO_CODE_SFT 4

#define	GSBI_CTL_PROTO_CODE_MSK 0x7

#define	GSBI_HCLK_CTL_GATE_ENA 6

#define	GSBI_HCLK_CTL_BRANCH_ENA 4

#define	GSBI_QUP_APPS_M_SHFT 16

#define	GSBI_QUP_APPS_M_MASK 0xFF

#define	GSBI_QUP_APPS_D_SHFT 0

#define	GSBI_QUP_APPS_D_MASK 0xFF

#define	GSBI_QUP_APPS_N_SHFT 16

#define	GSBI_QUP_APPS_N_MASK 0xFF

#define	GSBI_QUP_APPS_ROOT_ENA_SFT 11

#define	GSBI_QUP_APPS_BRANCH_ENA_SFT 9

#define	GSBI_QUP_APPS_MNCTR_EN_SFT 8

#define	GSBI_QUP_APPS_MNCTR_MODE_MSK 0x3

#define	GSBI_QUP_APPS_MNCTR_MODE_SFT 5

#define	GSBI_QUP_APPS_PRE_DIV_MSK 0x3

#define	GSBI_QUP_APPS_PRE_DIV_SFT 3

#define	GSBI_QUP_APPS_SRC_SEL_MSK 0x7

#define	GSBI_QUP_APSS_MD_REG(gsbi_n)

#define	GSBI_QUP_APSS_NS_REG(gsbi_n)

#define	GSBI_HCLK_CTL(n)

Macro Definition Documentation

◆ APCS_WDT0_BARK_TIME

#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C)

Definition at line 30 of file iomap.h.

◆ APCS_WDT0_BITE_TIME

#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C)

Definition at line 31 of file iomap.h.

◆ APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE

#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820)

Definition at line 33 of file iomap.h.

◆ APCS_WDT0_EN

#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)

Definition at line 28 of file iomap.h.

◆ APCS_WDT0_RST

#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038)

Definition at line 29 of file iomap.h.

◆ clrsetbits32_i

#define clrsetbits32_i	(	addr,
		clear,
		set
	)	clrsetbits32(((void *)(addr)), (clear), (set))

Definition at line 16 of file iomap.h.

◆ DGT_CLEAR

#define DGT_CLEAR DGT_REG(0x000C)

Definition at line 48 of file iomap.h.

◆ DGT_CLK_CTL

#define DGT_CLK_CTL DGT_REG(0x0010)

Definition at line 49 of file iomap.h.

◆ DGT_COUNT_VAL

#define DGT_COUNT_VAL DGT_REG(0x0004)

Definition at line 46 of file iomap.h.

◆ DGT_ENABLE

#define DGT_ENABLE DGT_REG(0x0008)

Definition at line 47 of file iomap.h.

◆ DGT_MATCH_VAL

#define DGT_MATCH_VAL DGT_REG(0x0000)

Definition at line 45 of file iomap.h.

◆ DGT_REG

#define DGT_REG ( off ) (MSM_DGT_BASE + (off))

Definition at line 26 of file iomap.h.

◆ GPIO_CONFIG_ADDR

#define GPIO_CONFIG_ADDR ( x ) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)

Definition at line 59 of file iomap.h.

◆ GPIO_IN_OUT_ADDR

#define GPIO_IN_OUT_ADDR ( x ) (GPIO_CONFIG_ADDR(x) + 4)

Definition at line 60 of file iomap.h.

◆ GPT1_CLEAR

#define GPT1_CLEAR GPT_REG(0x0001C)

Definition at line 43 of file iomap.h.

◆ GPT1_COUNT_VAL

#define GPT1_COUNT_VAL GPT_REG(0x00014)

Definition at line 41 of file iomap.h.

◆ GPT1_ENABLE

#define GPT1_ENABLE GPT_REG(0x00018)

Definition at line 42 of file iomap.h.

◆ GPT1_MATCH_VAL

#define GPT1_MATCH_VAL GPT_REG(0x00010)

Definition at line 40 of file iomap.h.

◆ GPT_CLEAR

#define GPT_CLEAR GPT_REG(0x000C)

Definition at line 38 of file iomap.h.

◆ GPT_COUNT_VAL

#define GPT_COUNT_VAL GPT_REG(0x0004)

Definition at line 36 of file iomap.h.

◆ GPT_ENABLE

#define GPT_ENABLE GPT_REG(0x0008)

Definition at line 37 of file iomap.h.

◆ GPT_MATCH_VAL

#define GPT_MATCH_VAL GPT_REG(0x0000)

Definition at line 35 of file iomap.h.

◆ GPT_REG

#define GPT_REG ( off ) (MSM_GPT_BASE + (off))

Definition at line 25 of file iomap.h.

◆ GSBI1_BASE

#define GSBI1_BASE ((void *)0x12440000)

Definition at line 81 of file iomap.h.

◆ GSBI1_CTL_REG

#define GSBI1_CTL_REG (GSBI1_BASE + (0x0))

Definition at line 89 of file iomap.h.

◆ GSBI2_BASE

#define GSBI2_BASE ((void *)0x12480000)

Definition at line 82 of file iomap.h.

◆ GSBI2_CTL_REG

#define GSBI2_CTL_REG (GSBI2_BASE + (0x0))

Definition at line 90 of file iomap.h.

◆ GSBI3_BASE

#define GSBI3_BASE ((void *)0x16200000)

Definition at line 83 of file iomap.h.

◆ GSBI3_CTL_REG

#define GSBI3_CTL_REG (GSBI3_BASE + (0x0))

Definition at line 91 of file iomap.h.

◆ GSBI4_BASE

#define GSBI4_BASE ((void *)0x16300000)

Definition at line 84 of file iomap.h.

◆ GSBI4_CTL_REG

#define GSBI4_CTL_REG (GSBI4_BASE + (0x0))

Definition at line 92 of file iomap.h.

◆ GSBI5_BASE

#define GSBI5_BASE ((void *)0x1A200000)

Definition at line 85 of file iomap.h.

◆ GSBI5_CTL_REG

#define GSBI5_CTL_REG (GSBI5_BASE + (0x0))

Definition at line 93 of file iomap.h.

◆ GSBI6_BASE

#define GSBI6_BASE ((void *)0x16500000)

Definition at line 86 of file iomap.h.

◆ GSBI6_CTL_REG

#define GSBI6_CTL_REG (GSBI6_BASE + (0x0))

Definition at line 94 of file iomap.h.

◆ GSBI7_BASE

#define GSBI7_BASE ((void *)0x16600000)

Definition at line 87 of file iomap.h.

◆ GSBI7_CTL_REG

#define GSBI7_CTL_REG (GSBI7_BASE + (0x0))

Definition at line 95 of file iomap.h.

◆ GSBI_4

#define GSBI_4 4

Definition at line 70 of file iomap.h.

◆ GSBI_CTL_PROTO_CODE_MSK

#define GSBI_CTL_PROTO_CODE_MSK 0x7

Definition at line 107 of file iomap.h.

◆ GSBI_CTL_PROTO_CODE_SFT

#define GSBI_CTL_PROTO_CODE_SFT 4

Definition at line 106 of file iomap.h.

◆ GSBI_CTL_PROTO_I2C

#define GSBI_CTL_PROTO_I2C 2

Definition at line 105 of file iomap.h.

◆ GSBI_HCLK_CTL

#define GSBI_HCLK_CTL ( n )

Value:

((MSM_CLK_CTL_BASE + 0x29C0) + \

(32*(n-1)))

MSM_CLK_CTL_BASE

#define MSM_CLK_CTL_BASE

Definition: iomap.h:19

Definition at line 129 of file iomap.h.

◆ GSBI_HCLK_CTL_BRANCH_ENA

#define GSBI_HCLK_CTL_BRANCH_ENA 4

Definition at line 109 of file iomap.h.

◆ GSBI_HCLK_CTL_GATE_ENA

#define GSBI_HCLK_CTL_GATE_ENA 6

Definition at line 108 of file iomap.h.

◆ GSBI_QUP1_BASE

#define GSBI_QUP1_BASE (GSBI1_BASE + 0x20000)

Definition at line 97 of file iomap.h.

◆ GSBI_QUP2_BASE

#define GSBI_QUP2_BASE (GSBI2_BASE + 0x20000)

Definition at line 98 of file iomap.h.

◆ GSBI_QUP3_BASE

#define GSBI_QUP3_BASE (GSBI3_BASE + 0x80000)

Definition at line 99 of file iomap.h.

◆ GSBI_QUP4_BASE

#define GSBI_QUP4_BASE (GSBI4_BASE + 0x80000)

Definition at line 100 of file iomap.h.

◆ GSBI_QUP5_BASE

#define GSBI_QUP5_BASE (GSBI5_BASE + 0x80000)

Definition at line 101 of file iomap.h.

◆ GSBI_QUP6_BASE

#define GSBI_QUP6_BASE (GSBI6_BASE + 0x80000)

Definition at line 102 of file iomap.h.

◆ GSBI_QUP7_BASE

#define GSBI_QUP7_BASE (GSBI7_BASE + 0x80000)

Definition at line 103 of file iomap.h.

◆ GSBI_QUP_APPS_BRANCH_ENA_SFT

#define GSBI_QUP_APPS_BRANCH_ENA_SFT 9

Definition at line 117 of file iomap.h.

◆ GSBI_QUP_APPS_D_MASK

#define GSBI_QUP_APPS_D_MASK 0xFF

Definition at line 113 of file iomap.h.

◆ GSBI_QUP_APPS_D_SHFT

#define GSBI_QUP_APPS_D_SHFT 0

Definition at line 112 of file iomap.h.

◆ GSBI_QUP_APPS_M_MASK

#define GSBI_QUP_APPS_M_MASK 0xFF

Definition at line 111 of file iomap.h.

◆ GSBI_QUP_APPS_M_SHFT

#define GSBI_QUP_APPS_M_SHFT 16

Definition at line 110 of file iomap.h.

◆ GSBI_QUP_APPS_MNCTR_EN_SFT

#define GSBI_QUP_APPS_MNCTR_EN_SFT 8

Definition at line 118 of file iomap.h.

◆ GSBI_QUP_APPS_MNCTR_MODE_MSK

#define GSBI_QUP_APPS_MNCTR_MODE_MSK 0x3

Definition at line 119 of file iomap.h.

◆ GSBI_QUP_APPS_MNCTR_MODE_SFT

#define GSBI_QUP_APPS_MNCTR_MODE_SFT 5

Definition at line 120 of file iomap.h.

◆ GSBI_QUP_APPS_N_MASK

#define GSBI_QUP_APPS_N_MASK 0xFF

Definition at line 115 of file iomap.h.

◆ GSBI_QUP_APPS_N_SHFT

#define GSBI_QUP_APPS_N_SHFT 16

Definition at line 114 of file iomap.h.

◆ GSBI_QUP_APPS_PRE_DIV_MSK

#define GSBI_QUP_APPS_PRE_DIV_MSK 0x3

Definition at line 121 of file iomap.h.

◆ GSBI_QUP_APPS_PRE_DIV_SFT

#define GSBI_QUP_APPS_PRE_DIV_SFT 3

Definition at line 122 of file iomap.h.

◆ GSBI_QUP_APPS_ROOT_ENA_SFT

#define GSBI_QUP_APPS_ROOT_ENA_SFT 11

Definition at line 116 of file iomap.h.

◆ GSBI_QUP_APPS_SRC_SEL_MSK

#define GSBI_QUP_APPS_SRC_SEL_MSK 0x7

Definition at line 123 of file iomap.h.

◆ GSBI_QUP_APSS_MD_REG

#define GSBI_QUP_APSS_MD_REG ( gsbi_n )

Value:

((MSM_CLK_CTL_BASE + 0x29c8) + \

(32*(gsbi_n-1)))

Definition at line 125 of file iomap.h.

◆ GSBI_QUP_APSS_NS_REG

#define GSBI_QUP_APSS_NS_REG ( gsbi_n )

Value:

((MSM_CLK_CTL_BASE + 0x29cc) + \

(32*(gsbi_n-1)))

Definition at line 127 of file iomap.h.

◆ MSM_CLK_CTL_BASE

#define MSM_CLK_CTL_BASE ((void *)0x00900000)

Definition at line 19 of file iomap.h.

◆ MSM_DGT_BASE

#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)

Definition at line 23 of file iomap.h.

◆ MSM_GPT_BASE

#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)

Definition at line 22 of file iomap.h.

◆ MSM_TMR_BASE

#define MSM_TMR_BASE ((void *)0x0200A000)

Definition at line 21 of file iomap.h.

◆ readl_i

#define readl_i ( a ) read32((const void *)(a))

Definition at line 14 of file iomap.h.

◆ RPM_FW_MAGIC_NUM

#define RPM_FW_MAGIC_NUM 0x4D505242

Definition at line 56 of file iomap.h.

◆ RPM_INT

#define RPM_INT ((void *)0x63020)

Definition at line 52 of file iomap.h.

◆ RPM_INT_ACK

#define RPM_INT_ACK ((void *)0x63060)

Definition at line 53 of file iomap.h.

◆ RPM_SIGNAL_COOKIE

#define RPM_SIGNAL_COOKIE ((void *)0x47C20)

Definition at line 54 of file iomap.h.

◆ RPM_SIGNAL_ENTRY

#define RPM_SIGNAL_ENTRY ((void *)0x47C24)

Definition at line 55 of file iomap.h.

◆ TLMM_BASE_ADDR

#define TLMM_BASE_ADDR ((void *)0x00800000)

Definition at line 58 of file iomap.h.

◆ UART1_DM_BASE

#define UART1_DM_BASE 0x12450000

Definition at line 71 of file iomap.h.

◆ UART2_DM_BASE [1/2]

#define UART2_DM_BASE 0x12490000

Definition at line 78 of file iomap.h.

◆ UART2_DM_BASE [2/2]

#define UART2_DM_BASE 0x12490000

Definition at line 78 of file iomap.h.

◆ UART4_DM_BASE

#define UART4_DM_BASE 0x16340000

Definition at line 75 of file iomap.h.

◆ UART_GSBI1_BASE

#define UART_GSBI1_BASE 0x12440000

Definition at line 72 of file iomap.h.

◆ UART_GSBI2_BASE [1/2]

#define UART_GSBI2_BASE 0x12480000

Definition at line 79 of file iomap.h.

◆ UART_GSBI2_BASE [2/2]

#define UART_GSBI2_BASE 0x12480000

Definition at line 79 of file iomap.h.

◆ UART_GSBI4_BASE

#define UART_GSBI4_BASE 0x16300000

Definition at line 76 of file iomap.h.

◆ USB_HOST1_DWC3_BASE

#define USB_HOST1_DWC3_BASE 0x1100C100

Definition at line 67 of file iomap.h.

◆ USB_HOST1_PHY_BASE

#define USB_HOST1_PHY_BASE 0x110F8800

Definition at line 68 of file iomap.h.

◆ USB_HOST1_XHCI_BASE

#define USB_HOST1_XHCI_BASE 0x11000000

Definition at line 66 of file iomap.h.

◆ USB_HOST2_DWC3_BASE

#define USB_HOST2_DWC3_BASE 0x1000C100

Definition at line 64 of file iomap.h.

◆ USB_HOST2_PHY_BASE

#define USB_HOST2_PHY_BASE 0x100F8800

Definition at line 65 of file iomap.h.

◆ USB_HOST2_XHCI_BASE

#define USB_HOST2_XHCI_BASE 0x10000000

Definition at line 63 of file iomap.h.

◆ writel_i

#define writel_i	(	v,
		a
	)	write32((void *)a, v)

Definition at line 15 of file iomap.h.

Macros

Macro Definition Documentation

◆ APCS_WDT0_BARK_TIME

◆ APCS_WDT0_BITE_TIME

◆ APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE

◆ APCS_WDT0_EN

◆ APCS_WDT0_RST

◆ clrsetbits32_i

◆ DGT_CLEAR

◆ DGT_CLK_CTL

◆ DGT_COUNT_VAL

◆ DGT_ENABLE

◆ DGT_MATCH_VAL

◆ DGT_REG

◆ GPIO_CONFIG_ADDR

◆ GPIO_IN_OUT_ADDR

◆ GPT1_CLEAR

◆ GPT1_COUNT_VAL

◆ GPT1_ENABLE

◆ GPT1_MATCH_VAL

◆ GPT_CLEAR

◆ GPT_COUNT_VAL

◆ GPT_ENABLE

◆ GPT_MATCH_VAL

◆ GPT_REG

◆ GSBI1_BASE

◆ GSBI1_CTL_REG

◆ GSBI2_BASE

◆ GSBI2_CTL_REG

◆ GSBI3_BASE

◆ GSBI3_CTL_REG

◆ GSBI4_BASE

◆ GSBI4_CTL_REG

◆ GSBI5_BASE

◆ GSBI5_CTL_REG

◆ GSBI6_BASE

◆ GSBI6_CTL_REG

◆ GSBI7_BASE

◆ GSBI7_CTL_REG

◆ GSBI_4

◆ GSBI_CTL_PROTO_CODE_MSK

◆ GSBI_CTL_PROTO_CODE_SFT

◆ GSBI_CTL_PROTO_I2C

◆ GSBI_HCLK_CTL

◆ GSBI_HCLK_CTL_BRANCH_ENA

◆ GSBI_HCLK_CTL_GATE_ENA

◆ GSBI_QUP1_BASE

◆ GSBI_QUP2_BASE

◆ GSBI_QUP3_BASE

◆ GSBI_QUP4_BASE

◆ GSBI_QUP5_BASE

◆ GSBI_QUP6_BASE

◆ GSBI_QUP7_BASE

◆ GSBI_QUP_APPS_BRANCH_ENA_SFT

◆ GSBI_QUP_APPS_D_MASK

◆ GSBI_QUP_APPS_D_SHFT

◆ GSBI_QUP_APPS_M_MASK

◆ GSBI_QUP_APPS_M_SHFT

◆ GSBI_QUP_APPS_MNCTR_EN_SFT

◆ GSBI_QUP_APPS_MNCTR_MODE_MSK

◆ GSBI_QUP_APPS_MNCTR_MODE_SFT

◆ GSBI_QUP_APPS_N_MASK

◆ GSBI_QUP_APPS_N_SHFT

◆ GSBI_QUP_APPS_PRE_DIV_MSK

◆ GSBI_QUP_APPS_PRE_DIV_SFT

◆ GSBI_QUP_APPS_ROOT_ENA_SFT

◆ GSBI_QUP_APPS_SRC_SEL_MSK

◆ GSBI_QUP_APSS_MD_REG

◆ GSBI_QUP_APSS_NS_REG

◆ MSM_CLK_CTL_BASE

◆ MSM_DGT_BASE

◆ MSM_GPT_BASE

◆ MSM_TMR_BASE

◆ readl_i

◆ RPM_FW_MAGIC_NUM

◆ RPM_INT

◆ RPM_INT_ACK

◆ RPM_SIGNAL_COOKIE

◆ RPM_SIGNAL_ENTRY

◆ TLMM_BASE_ADDR