coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_MEDIATEK_MT8183_GPIO_H
4 #define SOC_MEDIATEK_MT8183_GPIO_H
5 
6 #include <soc/addressmap.h>
7 #include <soc/gpio_common.h>
8 #include <types.h>
9 #include <soc/spi_common.h>
10 
11 enum {
12  MAX_GPIO_REG_BITS = 32,
13  MAX_GPIO_MODE_PER_REG = 8,
14  GPIO_MODE_BITS = 4,
15 };
16 
17 #define IOCFG_TO_GPIO_BASE(x) ((x >> 16) & 0xff)
18 #define GPIO_TO_IOCFG_BASE(x) ((void *)(IOCFG_RT_BASE & 0xff000000) + \
19  ((x) << 16))
20 
21 #define PIN(id, name, flag, bit, base, offset, \
22  func1, func2, func3, func4, func5, func6, func7) \
23  PAD_##name##_ID = id, \
24  PAD_##name##_FLAG = flag, \
25  PAD_##name##_BIT = bit, \
26  PAD_##name##_BASE = IOCFG_TO_GPIO_BASE(base), \
27  PAD_##name##_OFFSET = offset, \
28  PAD_##name##_FUNC_##func1 = 1, \
29  PAD_##name##_FUNC_##func2 = 2, \
30  PAD_##name##_FUNC_##func3 = 3, \
31  PAD_##name##_FUNC_##func4 = 4, \
32  PAD_##name##_FUNC_##func5 = 5, \
33  PAD_##name##_FUNC_##func6 = 6, \
34  PAD_##name##_FUNC_##func7 = 7
35 
36 #define GPIO(name) ((gpio_t){ \
37  .id = PAD_##name##_ID, \
38  .flag = PAD_##name##_FLAG, \
39  .bit = PAD_##name##_BIT, \
40  .base = PAD_##name##_BASE, \
41  .offset = PAD_##name##_OFFSET \
42  })
43 
44 enum {
45  PIN(0, EINT0, 0, 6, IOCFG_RM_BASE, 0x00,
46  MRG_SYNC, PCM0_SYNC, TP_GPIO0_AO,
47  SRCLKENAI0, SCP_SPI2_CS, I2S3_MCK, SPI2_CSB),
48  PIN(1, EINT1, 0, 7, IOCFG_RM_BASE, 0x00,
49  MRG_CLK, PCM0_CLK, TP_GPIO1_AO,
50  CLKM3, SCP_SPI2_MO, I2S3_BCK, SPI2_MO),
51  PIN(2, EINT2, 0, 8, IOCFG_RM_BASE, 0x00,
52  MRG_DO, PCM0_DO, TP_GPIO2_AO,
53  SCL6, SCP_SPI2_CK, I2S3_LRCK, SPI2_CLK),
54  PIN(3, EINT3, 0, 9, IOCFG_RM_BASE, 0x00,
55  MRG_DI, PCM0_DI, TP_GPIO3_AO,
56  DA6, TDM_MCK, I2S3_DO, SCP_VREQ_VAO),
57  PIN(4, EINT4, 0, 11, IOCFG_RM_BASE, 0x00,
58  PWM_B, I2S0_MCK, SSPM_UTXD_AO,
59  MD_URXD1, TDM_BCK, TP_GPIO4_AO, DAP_MD32_SWD),
60  PIN(5, EINT5, 0, 12, IOCFG_RM_BASE, 0x00,
61  PWM_C, I2S0_BCK, SSPM_URXD_AO,
62  MD_UTXD1, TDM_LRCK, TP_GPIO5_AO, DAP_MD32_SWCK),
63  PIN(6, EINT6, 0, 13, IOCFG_RM_BASE, 0x00,
64  PWM_A, I2S0_LRCK, IDDIG,
65  MD_URXD0, TDM_DATA0, TP_GPIO6_AO, CMFLASH),
66  PIN(7, EINT7, 0, 14, IOCFG_RM_BASE, 0x00,
67  SPI1_B_MI, I2S0_DI, USB_DRVVBUS,
68  MD_UTXD0, TDM_DATA1, TP_GPIO7_AO, DVFSRC_EXT_REQ),
69  PIN(8, EINT8, 0, 0, IOCFG_RM_BASE, 0x00,
70  SPI1_B_CSB, ANT_SEL3, SCL7,
71  CONN_MCU_TRST_B, TDM_DATA2, MD_INT0, JTRSTN_SEL1),
72  PIN(9, EINT9, 0, 26, IOCFG_RM_BASE, 0x00,
73  SPI1_B_MO, ANT_SEL4, CMMCLK2,
74  CONN_MCU_DBGACK_N, SSPM_JTAG_TRSTN, IO_JTAG_TRSTN, DBG_MON_B10),
75  PIN(10, EINT10, 0, 27, IOCFG_RM_BASE, 0x00,
76  SPI1_B_CLK, ANT_SEL5, CMMCLK3,
77  CONN_MCU_DBGI_N, TDM_DATA3, EXT_FRAME_SYNC, DBG_MON_B11),
78  PIN(11, SCL6, 0, 10, IOCFG_LT_BASE, 0x00,
79  TP_URXD1_AO, IDDIG, SCL6,
80  UCTS1, UCTS0, SRCLKENAI1, I2S5_MCK),
81  PIN(12, SDA6, 0, 17, IOCFG_LT_BASE, 0x00,
82  TP_UTXD1_AO, USB_DRVVBUS, SDA6,
83  URTS1, URTS0, I2S2_DI2, I2S5_BCK),
84  PIN(13, DPI_D0, 0, 6, IOCFG_LM_BASE, 0x00,
85  DBPI_D0, SPI5_MI, PCM0_SYNC,
86  MD_URXD0, ANT_SEL3, I2S0_MCK, DBG_MON_B15),
87  PIN(14, DPI_D1, 0, 7, IOCFG_LM_BASE, 0x00,
88  DBPI_D1, SPI5_CSB, PCM0_CLK,
89  MD_UTXD0, ANT_SEL4, I2S0_BCK, DBG_MON_B16),
90  PIN(15, DPI_D2, 0, 8, IOCFG_LM_BASE, 0x00,
91  DBPI_D2, SPI5_MO, PCM0_DO,
92  MD_URXD1, ANT_SEL5, I2S0_LRCK, DBG_MON_B17),
93  PIN(16, DPI_D3, 0, 9, IOCFG_LM_BASE, 0x00,
94  DBPI_D3, SPI5_CLK, PCM0_DI,
95  MD_UTXD1, ANT_SEL6, I2S0_DI, DBG_MON_B23),
96  PIN(17, DPI_D4, 0, 10, IOCFG_LM_BASE, 0x00,
97  DBPI_D4, SPI4_MI, CONN_MCU_TRST_B,
98  MD_INT0, ANT_SEL7, I2S3_MCK, DBG_MON_A1),
99  PIN(18, DPI_D5, 0, 11, IOCFG_LM_BASE, 0x00,
100  DBPI_D5, SPI4_CSB, CONN_MCU_DBGI_N,
101  MD_INT0, SCP_VREQ_VAO, I2S3_BCK, DBG_MON_A2),
102  PIN(19, DPI_D6, 0, 12, IOCFG_LM_BASE, 0x00,
103  DBPI_D6, SPI4_MO, CONN_MCU_TDO,
104  MD_INT2_C2K_UIM1_HOT_PLUG, URXD1, I2S3_LRCK, DBG_MON_A3),
105  PIN(20, DPI_D7, 0, 13, IOCFG_LM_BASE, 0x00,
106  DBPI_D7, SPI4_CLK, CONN_MCU_DBGACK_N,
107  MD_INT1_C2K_UIM0_HOT_PLUG, UTXD1, I2S3_DO, DBG_MON_A19),
108  PIN(21, DPI_D8, 0, 14, IOCFG_LM_BASE, 0x00,
109  DBPI_D8, SPI3_MI, CONN_MCU_TMS,
110  DAP_MD32_SWD, CONN_MCU_AICE_TMSC, I2S2_MCK, DBG_MON_B5),
111  PIN(22, DPI_D9, 0, 15, IOCFG_LM_BASE, 0x00,
112  DBPI_D9, SPI3_CSB, CONN_MCU_TCK,
113  DAP_MD32_SWCK, CONN_MCU_AICE_TCKC, I2S2_BCK, DBG_MON_B6),
114  PIN(23, DPI_D10, 0, 16, IOCFG_LM_BASE, 0x00,
115  DBPI_D10, SPI3_MO, CONN_MCU_TDI,
116  UCTS1, EXT_FRAME_SYNC, I2S2_LRCK, DBG_MON_B7),
117  PIN(24, DPI_D11, 0, 17, IOCFG_LM_BASE, 0x00,
118  DBPI_D11, SPI3_CLK, SRCLKENAI0,
119  URTS1, IO_JTAG_TCK, I2S2_DI, DBG_MON_B31),
120  PIN(25, DPI_HSYNC, 0, 18, IOCFG_LM_BASE, 0x00,
121  DBPI_HSYNC, ANT_SEL0, SCL6,
122  KPCOL2, IO_JTAG_TMS, I2S1_MCK, DBG_MON_B0),
123  PIN(26, DPI_VSYNC, 0, 19, IOCFG_LM_BASE, 0x00,
124  DBPI_VSYNC, ANT_SEL1, SDA6,
125  KPROW2, IO_JTAG_TDI, I2S1_BCK, DBG_MON_B1),
126  PIN(27, DPI_DE, 0, 20, IOCFG_LM_BASE, 0x00,
127  DBPI_DE, ANT_SEL2, SCL7,
128  DMIC_CLK, IO_JTAG_TDO, I2S1_LRCK, DBG_MON_B9),
129  PIN(28, DPI_CK, 0, 21, IOCFG_LM_BASE, 0x00,
130  DBPI_CK, DVFSRC_EXT_REQ, SDA7,
131  DMIC_DAT, IO_JTAG_TRSTN, I2S1_DO, DBG_MON_B32),
132  PIN(29, MSDC1_CLK, 1, 0, IOCFG_LM_BASE, 0xc0,
133  MSDC1_CLK, IO_JTAG_TCK, UDI_TCK,
134  CONN_DSP_JCK, SSPM_JTAG_TCK, PCM1_CLK, DBG_MON_A6),
135  PIN(30, MSDC1_DAT3, 1, 4, IOCFG_LM_BASE, 0xc0,
136  MSDC1_DAT3, DAP_MD32_SWD, CONN_MCU_AICE_TMSC,
137  CONN_DSP_JINTP, SSPM_JTAG_TRSTN, PCM1_DI, DBG_MON_A7),
138  PIN(31, MSDC1_CMD, 1, 8, IOCFG_LM_BASE, 0xc0,
139  MSDC1_CMD, IO_JTAG_TMS, UDI_TMS,
140  CONN_DSP_JMS, SSPM_JTAG_TMS, PCM1_SYNC, DBG_MON_A8),
141  PIN(32, MSDC1_DAT0, 1, 12, IOCFG_LM_BASE, 0xc0,
142  MSDC1_DAT0, IO_JTAG_TDI, UDI_TDI,
143  CONN_DSP_JDI, SSPM_JTAG_TDI, PCM1_DO0, DBG_MON_A9),
144  PIN(33, MSDC1_DAT2, 1, 16, IOCFG_LM_BASE, 0xc0,
145  MSDC1_DAT2, IO_JTAG_TRSTN, UDI_NTRST,
146  DAP_MD32_SWCK, CONN_MCU_AICE_TCKC, PCM1_DO2, DBG_MON_A10),
147  PIN(34, MSDC1_DAT1, 1, 20, IOCFG_LM_BASE, 0xc0,
148  MSDC1_DAT1, IO_JTAG_TDO, UDI_TDO,
149  CONN_DSP_JDO, SSPM_JTAG_TDO, PCM1_DO1, DBG_MON_A11),
150  PIN(35, SIM2_SIO, 1, 0, IOCFG_LB_BASE, 0xc0,
151  MD1_SIM2_SIO, CCU_JTAG_TDO, MD1_SIM1_SIO,
152  RES4, SCP_JTAG_TDO, CONN_DSP_JMS, DBG_MON_A28),
153  PIN(36, SIM2_SRST, 1, 4, IOCFG_LB_BASE, 0xc0,
154  MD1_SIM2_SRST, CCU_JTAG_TMS, MD1_SIM1_SRST,
155  CONN_MCU_AICE_TMSC, SCP_JTAG_TMS, CONN_DSP_JINTP, DBG_MON_A29),
156  PIN(37, SIM2_SCLK, 1, 8, IOCFG_LB_BASE, 0xc0,
157  MD1_SIM2_SCLK, CCU_JTAG_TDI, MD1_SIM1_SCLK,
158  RES4, SCP_JTAG_TDI, CONN_DSP_JDO, DBG_MON_A30),
159  PIN(38, SIM1_SCLK, 1, 12, IOCFG_LB_BASE, 0xc0,
160  MD1_SIM1_SCLK, RES2, MD1_SIM2_SCLK,
161  CONN_MCU_AICE_TCKC, RES5, RES6, DBG_MON_A20),
162  PIN(39, SIM1_SRST, 1, 16, IOCFG_LB_BASE, 0xc0,
163  MD1_SIM1_SRST, CCU_JTAG_TCK, MD1_SIM2_SRST,
164  RES4, SCP_JTAG_TCK, CONN_DSP_JCK, DBG_MON_A31),
165  PIN(40, SIM1_SIO, 1, 20, IOCFG_LB_BASE, 0xc0,
166  MD1_SIM1_SIO, CCU_JTAG_TRST, MD1_SIM2_SIO,
167  RES4, SCP_JTAG_TRSTN, CONN_DSP_JDI, DBG_MON_A32),
168  PIN(41, IDDIG, 1, 24, IOCFG_LB_BASE, 0xc0,
169  IDDIG, URXD1, UCTS0,
170  SSPM_UTXD_AO, EXT_FRAME_SYNC, DMIC_CLK, RES7),
171  PIN(42, DRVBUS, 1, 28, IOCFG_LB_BASE, 0xc0,
172  USB_DRVVBUS, UTXD1, URTS0,
173  SSPM_URXD_AO, EXT_FRAME_SYNC, DMIC_DAT, RES7),
174  PIN(43, DISP_PWM, 0, 8, IOCFG_LB_BASE, 0x00,
175  DISP_PWM, RES2, RES3,
176  RES4, RES5, RES6, RES7),
177  PIN(44, DSI_TE, 0, 9, IOCFG_LB_BASE, 0x00,
178  DSI_TE, RES2, RES3,
179  RES4, RES5, RES6, RES7),
180  PIN(45, LCM_RST, 0, 10, IOCFG_LB_BASE, 0x00,
181  LCM_RST, RES2, RES3,
182  RES4, RES5, RES6, RES7),
183  PIN(46, INT_SIM2, 0, 11, IOCFG_LB_BASE, 0x00,
184  MD_INT2_C2K_UIM1_HOT_PLUG, URXD1, UCTS1,
185  CCU_UTXD_AO, TP_UCTS1_AO, IDDIG, I2S5_LRCK),
186  PIN(47, INT_SIM1, 0, 12, IOCFG_LB_BASE, 0x00,
187  MD_INT1_C2K_UIM0_HOT_PLUG, UTXD1, URTS1,
188  CCU_URXD_AO, TP_URTS1_AO, USB_DRVVBUS, I2S5_DO),
189  PIN(48, SCL5, 0, 13, IOCFG_LB_BASE, 0x00,
190  SCL5, RES2, RES3,
191  RES4, RES5, RES6, RES7),
192  PIN(49, SDA5, 0, 14, IOCFG_LB_BASE, 0x00,
193  SDA5, RES2, RES3,
194  RES4, RES5, RES6, RES7),
195  PIN(50, SCL3, 0, 0, IOCFG_BL_BASE, 0x00,
196  SCL3, RES2, RES3,
197  RES4, RES5, RES6, RES7),
198  PIN(51, SDA3, 0, 1, IOCFG_BL_BASE, 0x00,
199  SDA3, RES2, RES3,
200  RES4, RES5, RES6, RES7),
201  PIN(52, BPI_ANT2, 0, 2, IOCFG_BL_BASE, 0x00,
202  BPI_ANT2, RES2, RES3,
203  RES4, RES5, RES6, RES7),
204  PIN(53, BPI_ANT0, 0, 3, IOCFG_BL_BASE, 0x00,
205  BPI_ANT0, RES2, RES3,
206  RES4, RES5, RES6, RES7),
207  PIN(54, BPI_OLAT1, 0, 4, IOCFG_BL_BASE, 0x00,
208  BPI_OLAT1, RES2, RES3,
209  RES4, RES5, RES6, RES7),
210  PIN(55, BPI_BUS8, 0, 5, IOCFG_BL_BASE, 0x00,
211  BPI_BUS8, RES2, RES3,
212  RES4, RES5, RES6, RES7),
213  PIN(56, BPI_BUS9, 0, 6, IOCFG_BL_BASE, 0x00,
214  BPI_BUS9, SCL_6306, RES3,
215  RES4, RES5, RES6, RES7),
216  PIN(57, BPI_BUS10, 0, 7, IOCFG_BL_BASE, 0x00,
217  BPI_BUS10, SDA_6306, RES3,
218  RES4, RES5, RES6, RES7),
219  PIN(58, RFIC0_BSI_D2, 0, 8, IOCFG_BL_BASE, 0x00,
220  RFIC0_BSI_D2, SPM_BSI_D2, PWM_B,
221  RES4, RES5, RES6, RES7),
222  PIN(59, RFIC0_BSI_D1, 0, 9, IOCFG_BL_BASE, 0x00,
223  RFIC0_BSI_D1, SPM_BSI_D1, RES3,
224  RES4, RES5, RES6, RES7),
225  PIN(60, RFIC0_BSI_D0, 0, 10, IOCFG_BL_BASE, 0x00,
226  RFIC0_BSI_D0, SPM_BSI_D0, RES3,
227  RES4, RES5, RES6, RES7),
228  PIN(61, MISC_BSI_DO_1, 0, 0, IOCFG_RB_BASE, 0x00,
229  MIPI1_SDATA, RES2, RES3,
230  RES4, RES5, RES6, RES7),
231  PIN(62, MISC_BSI_CK_1, 0, 1, IOCFG_RB_BASE, 0x00,
232  MIPI1_SCLK, RES2, RES3,
233  RES4, RES5, RES6, RES7),
234  PIN(63, MISC_BSI_DO_0, 0, 2, IOCFG_RB_BASE, 0x00,
235  MIPI0_SDATA, RES2, RES3,
236  RES4, RES5, RES6, RES7),
237  PIN(64, MISC_BSI_CK_0, 0, 3, IOCFG_RB_BASE, 0x00,
238  MIPI0_SCLK, RES2, RES3,
239  RES4, RES5, RES6, RES7),
240  PIN(65, MISC_BSI_DO_3, 0, 4, IOCFG_RB_BASE, 0x00,
241  MIPI3_SDATA, BPI_OLAT2, RES3,
242  RES4, RES5, RES6, RES7),
243  PIN(66, MISC_BSI_CK_3, 0, 5, IOCFG_RB_BASE, 0x00,
244  MIPI3_SCLK, BPI_OLAT3, RES3,
245  RES4, RES5, RES6, RES7),
246  PIN(67, MISC_BSI_DO_2, 0, 6, IOCFG_RB_BASE, 0x00,
247  MIPI2_SDATA, RES2, RES3,
248  RES4, RES5, RES6, RES7),
249  PIN(68, MISC_BSI_CK_2, 0, 7, IOCFG_RB_BASE, 0x00,
250  MIPI2_SCLK, RES2, RES3,
251  RES4, RES5, RES6, RES7),
252  PIN(69, BPI_BUS7, 0, 8, IOCFG_RB_BASE, 0x00,
253  BPI_BUS7, RES2, RES3,
254  RES4, RES5, RES6, RES7),
255  PIN(70, BPI_BUS6, 0, 9, IOCFG_RB_BASE, 0x00,
256  BPI_BUS6, RES2, RES3,
257  RES4, RES5, RES6, RES7),
258  PIN(71, BPI_BUS5, 0, 10, IOCFG_RB_BASE, 0x00,
259  BPI_BUS5, RES2, RES3,
260  RES4, RES5, RES6, RES7),
261  PIN(72, BPI_BUS4, 0, 11, IOCFG_RB_BASE, 0x00,
262  BPI_BUS4, RES2, RES3,
263  RES4, RES5, RES6, RES7),
264  PIN(73, BPI_BUS3, 0, 12, IOCFG_RB_BASE, 0x00,
265  BPI_BUS3, RES2, RES3,
266  RES4, RES5, RES6, RES7),
267  PIN(74, BPI_BUS2, 0, 13, IOCFG_RB_BASE, 0x00,
268  BPI_BUS2, RES2, RES3,
269  RES4, RES5, RES6, RES7),
270  PIN(75, BPI_BUS1, 0, 14, IOCFG_RB_BASE, 0x00,
271  BPI_BUS1, RES2, RES3,
272  RES4, RES5, RES6, RES7),
273  PIN(76, BPI_BUS0, 0, 15, IOCFG_RB_BASE, 0x00,
274  BPI_BUS0, RES2, RES3,
275  RES4, RES5, RES6, RES7),
276  PIN(77, BPI_ANT1, 0, 16, IOCFG_RB_BASE, 0x00,
277  BPI_ANT1, RES2, RES3,
278  RES4, RES5, RES6, RES7),
279  PIN(78, BPI_OLAT0, 0, 17, IOCFG_RB_BASE, 0x00,
280  BPI_OLAT0, RES2, RES3,
281  RES4, RES5, RES6, RES7),
282  PIN(79, BPI_PA_VM1, 0, 18, IOCFG_RB_BASE, 0x00,
283  BPI_PA_VM1, MIPI4_SDATA, RES3,
284  RES4, RES5, RES6, RES7),
285  PIN(80, BPI_PA_VM0, 0, 19, IOCFG_RB_BASE, 0x00,
286  BPI_PA_VM0, MIPI4_SCLK, RES3,
287  RES4, RES5, RES6, RES7),
288  PIN(81, SDA1, 0, 20, IOCFG_RB_BASE, 0x00,
289  SDA1, RES2, RES3,
290  RES4, RES5, RES6, RES7),
291  PIN(82, SDA0, 0, 21, IOCFG_RB_BASE, 0x00,
292  SDA0, RES2, RES3,
293  RES4, RES5, RES6, RES7),
294  PIN(83, SCL0, 0, 22, IOCFG_RB_BASE, 0x00,
295  SCL0, RES2, RES3,
296  RES4, RES5, RES6, RES7),
297  PIN(84, SCL1, 0, 23, IOCFG_RB_BASE, 0x00,
298  SCL1, RES2, RES3,
299  RES4, RES5, RES6, RES7),
300  PIN(85, SPI_MI, 0, 24, IOCFG_RB_BASE, 0x00,
301  SPI0_MI, SCP_SPI0_MI, CLKM3,
302  I2S1_BCK, MFG_DFD_JTAG_TDO, DFD_TDO, JTDO_SEL1),
303  PIN(86, SPI_CSB, 0, 25, IOCFG_RB_BASE, 0x00,
304  SPI0_CSB, SCP_SPI0_CS, CLKM0,
305  I2S1_LRCK, MFG_DFD_JTAG_TMS, DFD_TMS, JTMS_SEL1),
306  PIN(87, SPI_MO, 0, 26, IOCFG_RB_BASE, 0x00,
307  SPI0_MO, SCP_SPI0_MO, SDA1,
308  I2S1_DO, MFG_DFD_JTAG_TDI, DFD_TDI, JTDI_SEL1),
309  PIN(88, SPI_CLK, 0, 27, IOCFG_RB_BASE, 0x00,
310  SPI0_CLK, SCP_SPI0_CK, SCL1,
311  I2S1_MCK, MFG_DFD_JTAG_TCK, DFD_TCK_XI, JTCK_SEL1),
312  PIN(89, SRCLKENAI, 0, 24, IOCFG_RM_BASE, 0x00,
313  SRCLKENAI0, PWM_C, I2S5_BCK,
314  ANT_SEL6, SDA8, CMVREF0, DBG_MON_A21),
315  PIN(90, PWM_A, 0, 1, IOCFG_RM_BASE, 0x00,
316  PWM_A, CMMCLK2, I2S5_LRCK,
317  SCP_VREQ_VAO, SCL8, PTA_RXD, DBG_MON_A22),
318  PIN(91, KPROW1, 1, 0, IOCFG_RM_BASE, 0xc0,
319  KPROW1, PWM_B, I2S5_DO,
320  ANT_SEL7, CMMCLK3, PTA_TXD, RES7),
321  PIN(92, KPROW0, 1, 4, IOCFG_RM_BASE, 0xc0,
322  KPROW0, RES2, RES3,
323  RES4, RES5, RES6, RES7),
324  PIN(93, KPCOL0, 1, 8, IOCFG_RM_BASE, 0xc0,
325  KPCOL0, RES2, RES3,
326  RES4, RES5, RES6, DBG_MON_B27),
327  PIN(94, KPCOL1, 1, 12, IOCFG_RM_BASE, 0xc0,
328  KPCOL1, I2S2_DI2, I2S5_MCK,
329  CMMCLK2, SCP_SPI2_MI, SRCLKENAI1, SPI2_MI),
330  PIN(95, URXD0, 0, 15, IOCFG_RM_BASE, 0x00,
331  URXD0, UTXD0, MD_URXD0,
332  MD_URXD1, SSPM_URXD_AO, CCU_URXD_AO, RES7),
333  PIN(96, UTXD0, 0, 17, IOCFG_RM_BASE, 0x00,
334  UTXD0, URXD0, MD_UTXD0,
335  MD_UTXD1, SSPM_UTXD_AO, CCU_UTXD_AO, DBG_MON_B2),
336  PIN(97, CAM_PDN0, 0, 18, IOCFG_RM_BASE, 0x00,
337  UCTS0, I2S2_MCK, IDDIG,
338  CONN_MCU_TDO, SSPM_JTAG_TDO, IO_JTAG_TDO, DBG_MON_B3),
339  PIN(98, CAM_PDN1, 0, 19, IOCFG_RM_BASE, 0x00,
340  URTS0, I2S2_BCK, USB_DRVVBUS,
341  CONN_MCU_TMS, SSPM_JTAG_TMS, IO_JTAG_TMS, DBG_MON_B4),
342  PIN(99, CAM_CLK0, 0, 20, IOCFG_RM_BASE, 0x00,
343  CMMCLK0, RES2, RES3,
344  CONN_MCU_AICE_TMSC, RES5, RES6, DBG_MON_B28),
345  PIN(100, CAM_CLK1, 0, 21, IOCFG_RM_BASE, 0x00,
346  CMMCLK1, PWM_C, MD_INT1_C2K_UIM0_HOT_PLUG,
347  CONN_MCU_AICE_TCKC, RES5, RES6, DBG_MON_B29),
348  PIN(101, CAM_RST0, 0, 22, IOCFG_RM_BASE, 0x00,
349  CLKM2, I2S2_LRCK, CMVREF1,
350  CONN_MCU_TCK, SSPM_JTAG_TCK, IO_JTAG_TCK, RES7),
351  PIN(102, CAM_RST1, 0, 23, IOCFG_RM_BASE, 0x00,
352  CLKM1, I2S2_DI, DVFSRC_EXT_REQ,
353  CONN_MCU_TDI, SSPM_JTAG_TDI, IO_JTAG_TDI, DBG_MON_B8),
354  PIN(103, SCL2, 0, 28, IOCFG_RM_BASE, 0x00,
355  SCL2, RES2, RES3,
356  RES4, RES5, RES6, RES7),
357  PIN(104, SDA2, 0, 29, IOCFG_RM_BASE, 0x00,
358  SDA2, RES2, RES3,
359  RES4, RES5, RES6, RES7),
360  PIN(105, SCL4, 0, 30, IOCFG_RM_BASE, 0x00,
361  SCL4, RES2, RES3,
362  RES4, RES5, RES6, RES7),
363  PIN(106, SDA4, 0, 31, IOCFG_RM_BASE, 0x00,
364  SDA4, RES2, RES3,
365  RES4, RES5, RES6, RES7),
366  PIN(107, CAM_PDN2, 0, 0, IOCFG_RT_BASE, 0x00,
367  DMIC_CLK, ANT_SEL0, CLKM0,
368  SDA7, EXT_FRAME_SYNC, PWM_A, DBG_MON_B12),
369  PIN(108, CAM_CLK2, 0, 1, IOCFG_RT_BASE, 0x00,
370  CMMCLK2, ANT_SEL1, CLKM1,
371  SCL8, DAP_MD32_SWD, PWM_B, DBG_MON_B13),
372  PIN(109, CAM_RST2, 0, 2, IOCFG_RT_BASE, 0x00,
373  DMIC_DAT, ANT_SEL2, CLKM2,
374  SDA8, DAP_MD32_SWCK, PWM_C, DBG_MON_B14),
375  PIN(110, CAM_PDN3, 0, 3, IOCFG_RT_BASE, 0x00,
376  SCL7, ANT_SEL0, TP_URXD1_AO,
377  USB_DRVVBUS, SRCLKENAI1, KPCOL2, URXD1),
378  PIN(111, CAM_CLK3, 0, 4, IOCFG_RT_BASE, 0x00,
379  CMMCLK3, ANT_SEL1, SRCLKENAI0,
380  SCP_VREQ_VAO, MD_INT2_C2K_UIM1_HOT_PLUG, RES6, DVFSRC_EXT_REQ),
381  PIN(112, CAM_RST3, 0, 5, IOCFG_RT_BASE, 0x00,
382  SDA7, ANT_SEL2, TP_UTXD1_AO,
383  IDDIG, AGPS_SYNC, KPROW2, UTXD1),
384  PIN(113, CONN_TOP_CLK, 0, 6, IOCFG_RT_BASE, 0x00,
385  CONN_TOP_CLK, RES2, SCL6,
386  AUXIF_CLK0, RES5, TP_UCTS1_AO, RES7),
387  PIN(114, CONN_TOP_DATA, 0, 7, IOCFG_RT_BASE, 0x00,
388  CONN_TOP_DATA, RES2, SDA6,
389  AUXIF_ST0, RES5, TP_URTS1_AO, RES7),
390  PIN(115, CONN_BT_CLK, 0, 8, IOCFG_RT_BASE, 0x00,
391  CONN_BT_CLK, UTXD1, PTA_TXD,
392  AUXIF_CLK1, DAP_MD32_SWD, TP_UTXD1_AO, RES7),
393  PIN(116, CONN_BT_DATA, 0, 9, IOCFG_RT_BASE, 0x00,
394  CONN_BT_DATA, IPU_JTAG_TRST, RES3,
395  AUXIF_ST1, DAP_MD32_SWCK, TP_URXD2_AO, DBG_MON_A0),
396  PIN(117, CONN_WF_CTRL0, 0, 10, IOCFG_RT_BASE, 0x00,
397  CONN_WF_HB0, IPU_JTAG_TDO, RES3,
398  RES4, RES5, TP_UTXD2_AO, DBG_MON_A4),
399  PIN(118, CONN_WF_CTRL1, 0, 11, IOCFG_RT_BASE, 0x00,
400  CONN_WF_HB1, IPU_JTAG_TDI, RES3,
401  RES4, SSPM_URXD_AO, TP_UCTS2_AO, DBG_MON_A5),
402  PIN(119, CONN_WF_CTRL2, 0, 12, IOCFG_RT_BASE, 0x00,
403  CONN_WF_HB2, IPU_JTAG_TCK, RES3,
404  RES4, SSPM_UTXD_AO, TP_URTS2_AO, RES7),
405  PIN(120, CONN_WB_PTA, 0, 13, IOCFG_RT_BASE, 0x00,
406  CONN_WB_PTA, IPU_JTAG_TMS, RES3,
407  RES4, CCU_URXD_AO, RES6, RES7),
408  PIN(121, CONN_HRST_B, 0, 14, IOCFG_RT_BASE, 0x00,
409  CONN_HRST_B, URXD1, PTA_RXD,
410  RES4, CCU_UTXD_AO, TP_URXD1_AO, RES7),
411  PIN(122, MSDC0_CMD, 1, 0, IOCFG_TL_BASE, 0xc0,
412  MSDC0_CMD, PWRMCU_URXD2_AO, ANT_SEL1,
413  RES4, RES5, RES6, DBG_MON_A12),
414  PIN(123, MSDC0_DAT0, 1, 4, IOCFG_TL_BASE, 0xc0,
415  MSDC0_DAT0, RES2, ANT_SEL0,
416  RES4, RES5, RES6, DBG_MON_A13),
417  PIN(124, MSDC0_CLK, 1, 8, IOCFG_TL_BASE, 0xc0,
418  MSDC0_CLK, RES2, RES3,
419  RES4, RES5, RES6, DBG_MON_A14),
420  PIN(125, MSDC0_DAT2, 1, 12, IOCFG_TL_BASE, 0xc0,
421  MSDC0_DAT2, RES2, MRG_CLK,
422  RES4, RES5, RES6, DBG_MON_A15),
423  PIN(126, MSDC0_DAT4, 1, 16, IOCFG_TL_BASE, 0xc0,
424  MSDC0_DAT4, RES2, ANT_SEL5,
425  RES4, RES5, UFS_MPHY_SCL, DBG_MON_A16),
426  PIN(127, MSDC0_DAT6, 1, 20, IOCFG_TL_BASE, 0xc0,
427  MSDC0_DAT6, RES2, ANT_SEL4,
428  RES4, RES5, UFS_MPHY_SDA, DBG_MON_A17),
429  PIN(128, MSDC0_DAT1, 1, 24, IOCFG_TL_BASE, 0xc0,
430  MSDC0_DAT1, RES2, ANT_SEL2,
431  RES4, RES5, UFS_UNIPRO_SDA, DBG_MON_A18),
432  PIN(129, MSDC0_DAT5, 1, 28, IOCFG_TL_BASE, 0xc0,
433  MSDC0_DAT5, RES2, ANT_SEL3,
434  RES4, RES5, UFS_UNIPRO_SCL, DBG_MON_A23),
435  PIN(130, MSDC0_DAT7, 1, 0, IOCFG_TL_BASE, 0xd0,
436  MSDC0_DAT7, RES2, MRG_DO,
437  RES4, RES5, RES6, DBG_MON_A24),
438  PIN(131, MSDC0_DSL, 1, 4, IOCFG_TL_BASE, 0xd0,
439  MSDC0_DSL, RES2, MRG_SYNC,
440  RES4, RES5, RES6, DBG_MON_A25),
441  PIN(132, MSDC0_DAT3, 1, 8, IOCFG_TL_BASE, 0xd0,
442  MSDC0_DAT3, RES2, MRG_DI,
443  RES4, RES5, RES6, DBG_MON_A26),
444  PIN(133, MSDC0_RSTB, 1, 12, IOCFG_TL_BASE, 0xd0,
445  MSDC0_RSTB, RES2, AGPS_SYNC,
446  RES4, RES5, RES6, DBG_MON_A27),
447  PIN(134, RTC32K_CK, 0, 0, IOCFG_LT_BASE, 0x00,
448  RTC32K_CK, RES2, RES3,
449  RES4, RES5, RES6, RES7),
450  PIN(135, WATCHDOG, 0, 1, IOCFG_LT_BASE, 0x00,
451  WATCHDOG, RES2, RES3,
452  RES4, RES5, RES6, RES7),
453  PIN(136, AUD_CLK_MOSI, 0, 2, IOCFG_LT_BASE, 0x00,
454  AUD_CLK_MOSI, AUD_CLK_MISO, I2S1_MCK,
455  RES4, RES5, UFS_UNIPRO_SCL, RES7),
456  PIN(137, AUD_SYNC_MOSI, 0, 3, IOCFG_LT_BASE, 0x00,
457  AUD_SYNC_MOSI, AUD_SYNC_MISO, I2S1_BCK,
458  RES4, RES5, RES6, RES7),
459  PIN(138, AUD_DAT_MOSI0, 0, 4, IOCFG_LT_BASE, 0x00,
460  AUD_DAT_MOSI0, AUD_DAT_MISO0, I2S1_LRCK,
461  RES4, RES5, RES6, DBG_MON_B24),
462  PIN(139, AUD_DAT_MOSI1, 0, 5, IOCFG_LT_BASE, 0x00,
463  AUD_DAT_MOSI1, AUD_DAT_MISO1, I2S1_DO,
464  RES4, RES5, UFS_MPHY_SDA, RES7),
465  PIN(140, AUD_CLK_MISO, 0, 6, IOCFG_LT_BASE, 0x00,
466  AUD_CLK_MISO, AUD_CLK_MOSI, I2S0_MCK,
467  RES4, RES5, UFS_UNIPRO_SDA, RES7),
468  PIN(141, AUD_SYNC_MISO, 0, 7, IOCFG_LT_BASE, 0x00,
469  AUD_SYNC_MISO, AUD_SYNC_MOSI, I2S0_BCK,
470  RES4, RES5, RES6, RES7),
471  PIN(142, AUD_DAT_MISO0, 0, 8, IOCFG_LT_BASE, 0x00,
472  AUD_DAT_MISO0, AUD_DAT_MOSI0, I2S0_LRCK,
473  VOW_DAT_MISO, RES5, RES6, DBG_MON_B25),
474  PIN(143, AUD_DAT_MISO1, 0, 9, IOCFG_LT_BASE, 0x00,
475  AUD_DAT_MISO1, AUD_DAT_MOSI1, I2S0_DI,
476  VOW_CLK_MISO, RES5, UFS_MPHY_SCL, DBG_MON_B26),
477  PIN(144, PWRAP_SPI0_MI, 0, 11, IOCFG_LT_BASE, 0x00,
478  PWRAP_SPI0_MI, PWRAP_SPI0_MO, RES3,
479  RES4, RES5, RES6, RES7),
480  PIN(145, PWRAP_SPI0_CSN, 0, 12, IOCFG_LT_BASE, 0x00,
481  PWRAP_SPI0_CSN, RES2, RES3,
482  RES4, RES5, RES6, RES7),
483  PIN(146, PWRAP_SPI0_MO, 0, 13, IOCFG_LT_BASE, 0x00,
484  PWRAP_SPI0_MO, PWRAP_SPI0_MI, RES3,
485  RES4, RES5, RES6, RES7),
486  PIN(147, PWRAP_SPI0_CK, 0, 14, IOCFG_LT_BASE, 0x00,
487  PWRAP_SPI0_CK, RES2, RES3,
488  RES4, RES5, RES6, RES7),
489  PIN(148, SRCLKENA0, 0, 15, IOCFG_LT_BASE, 0x00,
490  SRCLKENA0, RES2, RES3,
491  RES4, RES5, RES6, RES7),
492  PIN(149, SRCLKENA1, 0, 16, IOCFG_LT_BASE, 0x00,
493  SRCLKENA1, RES2, RES3,
494  RES4, RES5, RES6, RES7),
495  PIN(150, PERIPHERAL_EN0, 0, 18, IOCFG_LT_BASE, 0x00,
496  PWM_A, CMFLASH, CLKM0,
497  RES4, RES5, RES6, DBG_MON_B30),
498  PIN(151, PERIPHERAL_EN1, 0, 19, IOCFG_LT_BASE, 0x00,
499  PWM_B, CMVREF0, CLKM1,
500  RES4, RES5, RES6, DBG_MON_B20),
501  PIN(152, PERIPHERAL_EN2, 0, 20, IOCFG_LT_BASE, 0x00,
502  PWM_C, CMFLASH, CLKM2,
503  RES4, RES5, RES6, DBG_MON_B21),
504  PIN(153, PERIPHERAL_EN3, 0, 21, IOCFG_LT_BASE, 0x00,
505  PWM_A, CMVREF0, CLKM3,
506  RES4, RES5, RES6, DBG_MON_B22),
507  PIN(154, SCP_VREQ_VAO, 0, 22, IOCFG_LT_BASE, 0x00,
508  SCP_VREQ_VAO, DVFSRC_EXT_REQ, RES3,
509  RES4, RES5, RES6, DBG_MON_B18),
510  PIN(155, ANT_SEL0, 0, 23, IOCFG_LT_BASE, 0x00,
511  ANT_SEL0, DVFSRC_EXT_REQ, CMVREF1,
512  RES4, RES5, RES6, SCP_JTAG_TDI),
513  PIN(156, ANT_SEL1, 0, 24, IOCFG_LT_BASE, 0x00,
514  ANT_SEL1, SRCLKENAI0, SCL6,
515  KPCOL2, IDDIG, RES6, SCP_JTAG_TCK),
516  PIN(157, ANT_SEL2, 0, 25, IOCFG_LT_BASE, 0x00,
517  ANT_SEL2, SRCLKENAI1, SDA6,
518  KPROW2, USB_DRVVBUS, RES6, SCP_JTAG_TRSTN),
519  PIN(158, PERIPHERAL_EN6, 0, 26, IOCFG_LT_BASE, 0x00,
520  ANT_SEL3, RES2, RES3,
521  RES4, RES5, RES6, RES7),
522  PIN(159, PERIPHERAL_EN7, 0, 27, IOCFG_LT_BASE, 0x00,
523  ANT_SEL4, RES2, RES3,
524  RES4, RES5, RES6, RES7),
525  PIN(160, PERIPHERAL_EN8, 0, 28, IOCFG_LT_BASE, 0x00,
526  ANT_SEL5, RES2, RES3,
527  RES4, RES5, RES6, RES7),
528  PIN(161, SPI1_MI, 0, 0, IOCFG_LM_BASE, 0x00,
529  SPI1_A_MI, SCP_SPI1_MI, IDDIG,
530  ANT_SEL6, KPCOL2, PTA_RXD, DBG_MON_B19),
531  PIN(162, SPI1_CSB, 0, 1, IOCFG_LM_BASE, 0x00,
532  SPI1_A_CSB, SCP_SPI1_CS, USB_DRVVBUS,
533  ANT_SEL5, KPROW2, PTA_TXD, RES7),
534  PIN(163, SPI1_MO, 0, 2, IOCFG_LM_BASE, 0x00,
535  SPI1_A_MO, SCP_SPI1_MO, SDA1,
536  ANT_SEL4, CMMCLK2, DMIC_CLK, RES7),
537  PIN(164, SPI1_CLK, 0, 3, IOCFG_LM_BASE, 0x00,
538  SPI1_A_CLK, SCP_SPI1_CK, SCL1,
539  ANT_SEL3, CMMCLK3, DMIC_DAT, RES7),
540  PIN(165, PERIPHERAL_EN4, 0, 4, IOCFG_LM_BASE, 0x00,
541  PWM_B, CMMCLK2, SCP_VREQ_VAO,
542  RES4, RES5, TDM_MCK_2nd, SCP_JTAG_TDO),
543  PIN(166, PERIPHERAL_EN9, 0, 5, IOCFG_LM_BASE, 0x00,
544  ANT_SEL6, RES2, RES3,
545  RES4, RES5, RES6, RES7),
546  PIN(167, RFIC0_BSI_EN, 0, 11, IOCFG_BL_BASE, 0x00,
547  RFIC0_BSI_EN, SPM_BSI_EN, RES3,
548  RES4, RES5, RES6, RES7),
549  PIN(168, RFIC0_BSI_CK, 0, 12, IOCFG_BL_BASE, 0x00,
550  RFIC0_BSI_CK, SPM_BSI_CK, RES3,
551  RES4, RES5, RES6, RES7),
552  PIN(169, PERIPHERAL_EN5, 0, 13, IOCFG_BL_BASE, 0x00,
553  PWM_C, CMMCLK3, CMVREF1,
554  ANT_SEL7, AGPS_SYNC, TDM_BCK_2nd, SCP_JTAG_TMS),
555  PIN(170, I2S1_BCK, 0, 14, IOCFG_BL_BASE, 0x00,
556  I2S1_BCK, I2S3_BCK, SCL7,
557  I2S5_BCK, EXT_FRAME_SYNC, TDM_LRCK_2nd, ANT_SEL3),
558  PIN(171, I2S1_LRCK, 0, 15, IOCFG_BL_BASE, 0x00,
559  I2S1_LRCK, I2S3_LRCK, SDA7,
560  I2S5_LRCK, URXD1, TDM_DATA0_2nd, ANT_SEL4),
561  PIN(172, I2S1_DO, 0, 16, IOCFG_BL_BASE, 0x00,
562  I2S1_DO, I2S3_DO, SCL8,
563  I2S5_DO, UTXD1, TDM_DATA1_2nd, ANT_SEL5),
564  PIN(173, I2S1_MCK, 0, 17, IOCFG_BL_BASE, 0x00,
565  I2S1_MCK, I2S3_MCK, SDA8,
566  I2S5_MCK, UCTS0, TDM_DATA2_2nd, ANT_SEL6),
567  PIN(174, I2S2_DI, 0, 18, IOCFG_BL_BASE, 0x00,
568  I2S2_DI, I2S0_DI, DVFSRC_EXT_REQ,
569  I2S2_DI2, URTS0, TDM_DATA3_2nd, ANT_SEL7),
570  PIN(175, PERIPHERAL_EN12, 0, 19, IOCFG_BL_BASE, 0x00,
571  ANT_SEL7, RES2, RES3,
572  RES4, RES5, RES6, RES7),
573  PIN(176, PERIPHERAL_EN13, 0, 20, IOCFG_BL_BASE, 0x00,
574  RES1, RES2, RES3,
575  RES4, RES5, RES6, RES7),
576  PIN(177, PERIPHERAL_EN14, 0, 10, IOCFG_RM_BASE, 0x00,
577  RES1, RES2, RES3,
578  RES4, RES5, RES6, RES7),
579  PIN(178, PERIPHERAL_EN10, 0, 16, IOCFG_RM_BASE, 0x00,
580  RES1, RES2, RES3,
581  RES4, RES5, RES6, RES7),
582  PIN(179, PERIPHERAL_EN11, 0, 25, IOCFG_RM_BASE, 0x00,
583  RES1, RES2, RES3,
584  RES4, RES5, RES6, RES7),
585 };
586 
587 struct val_regs {
588  uint32_t val;
589  uint32_t set;
590  uint32_t rst;
591  uint32_t align;
592 };
593 
594 struct gpio_regs {
595  struct val_regs dir[6];
596  uint8_t rsv00[160];
597  struct val_regs dout[6];
598  uint8_t rsv01[160];
599  struct val_regs din[6];
600  uint8_t rsv02[160];
601  struct val_regs mode[23];
602 };
603 
604 check_member(gpio_regs, mode[22].val, 0x460);
605 
606 static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
607 void gpio_set_i2c_eh_rsel(void);
608 void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select,
609  unsigned int milliamps);
610 
611 #endif
SPI0_CLK
#define SPI0_CLK
Definition: gpio_soc_defs.h:104
SPI_CLK
@ SPI_CLK
Definition: pmif_spi.h:74
GPIO_BASE
#define GPIO_BASE
Definition: lpc.h:21
check_member
check_member(gpio_regs, msdc2_ctrl5, 0xcb0)
MAX_GPIO_MODE_PER_REG
@ MAX_GPIO_MODE_PER_REG
Definition: gpio.h:11
GPIO_MODE_BITS
@ GPIO_MODE_BITS
Definition: gpio.h:12
MAX_GPIO_REG_BITS
@ MAX_GPIO_REG_BITS
Definition: gpio.h:10
IOCFG_LT_BASE
@ IOCFG_LT_BASE
Definition: addressmap.h:46
IOCFG_LM_BASE
@ IOCFG_LM_BASE
Definition: addressmap.h:43
IOCFG_RB_BASE
@ IOCFG_RB_BASE
Definition: addressmap.h:40
IOCFG_TL_BASE
@ IOCFG_TL_BASE
Definition: addressmap.h:47
IOCFG_BL_BASE
@ IOCFG_BL_BASE
Definition: addressmap.h:44
IOCFG_RT_BASE
@ IOCFG_RT_BASE
Definition: addressmap.h:38
IOCFG_RM_BASE
@ IOCFG_RM_BASE
Definition: addressmap.h:39
IOCFG_LB_BASE
@ IOCFG_LB_BASE
Definition: addressmap.h:42
gpio_set_spi_driving
void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select, unsigned int milliamps)
Definition: gpio.c:123
gpio_set_i2c_eh_rsel
void gpio_set_i2c_eh_rsel(void)
Definition: gpio.c:100
mtk_gpio
static struct gpio_regs *const mtk_gpio
Definition: gpio.h:606
PIN
#define PIN(id, name, flag, bit, base, offset, func1, func2, func3, func4, func5, func6, func7)
Definition: gpio.h:21
spi_common.h
spi_pad_mask
spi_pad_mask
Definition: spi_common.h:45
uint32_t
unsigned int uint32_t
Definition: stdint.h:14
uint8_t
unsigned char uint8_t
Definition: stdint.h:8
bus
Definition: device.h:76
gpio_regs
Definition: gpio.h:312
gpio_regs::din
struct val_regs din[9]
Definition: gpio.h:322
gpio_regs::rsv00
uint8_t rsv00[112]
Definition: gpio.h:314
gpio_regs::mode
struct val_regs mode[27]
Definition: gpio.h:324
gpio_regs::rsv02
uint8_t rsv02[112]
Definition: gpio.h:318
gpio_regs::dout
struct val_regs dout[9]
Definition: gpio.h:320
gpio_regs::rsv01
uint8_t rsv01[112]
Definition: gpio.h:316
gpio_regs::dir
struct val_regs dir[9]
Definition: gpio.h:313
val_regs
Definition: gpio.h:305
val_regs::align
uint32_t align
Definition: gpio.h:309
val_regs::set
uint32_t set
Definition: gpio.h:307
val_regs::val
uint32_t val
Definition: gpio.h:306
val_regs::rst
uint32_t rst
Definition: gpio.h:308
val
u8 val
Definition: sys.c:300