coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
thermal.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <stdint.h>
4 #include <device/pci_def.h>
5 #include <spd.h>
6 
7 #include "delay.h"
8 #include "gm45.h"
9 
11 {
13  int x;
15  const chip_width_t width = sysinfo->dimms[x].chip_width;
17  if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x16)) {
18  mchbar_write32(CxDTPEW(x), 0x0d0b0403);
19  mchbar_write32(CxDTPEW(x) + 4, 0x060d);
20  mchbar_write32(CxDTAEW(x), 0x2d0b221a);
21  mchbar_write32(CxDTAEW(x) + 4, 0xc779956e);
22  } else
23  if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x8)) {
24  mchbar_write32(CxDTPEW(x), 0x06040101);
25  mchbar_write32(CxDTPEW(x) + 4, 0x0506);
26  if (size == CHIP_CAP_2G)
27  mchbar_write32(CxDTAEW(x), 0xa1071416);
28  else
29  mchbar_write32(CxDTAEW(x), 0x1a071416);
30  mchbar_write32(CxDTAEW(x) + 4, 0x7246643f);
31  } else
32  if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x16)) {
33  mchbar_write32(CxDTPEW(x), 0x06030100);
34  mchbar_write32(CxDTPEW(x) + 4, 0x0506);
35  mchbar_write32(CxDTAEW(x), 0x3e081714);
36  mchbar_write32(CxDTAEW(x) + 4, 0xbb79a171);
37  } else
38  if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x8)) {
39  if (size <= CHIP_CAP_512M)
40  mchbar_write32(CxDTPEW(x), 0x05050101);
41  else
42  mchbar_write32(CxDTPEW(x), 0x05060101);
43  mchbar_write32(CxDTPEW(x) + 4, 0x0503);
44  if (size == CHIP_CAP_2G) {
45  mchbar_write32(CxDTAEW(x), 0x57051010);
46  mchbar_write32(CxDTAEW(x) + 4, 0x5fd15dde);
47  } else
48  if (size == CHIP_CAP_1G) {
49  mchbar_write32(CxDTAEW(x), 0x3306130e);
50  mchbar_write32(CxDTAEW(x) + 4, 0x5763485d);
51  } else
52  if (size <= CHIP_CAP_512M) {
53  mchbar_write32(CxDTAEW(x), 0x1e08170d);
54  mchbar_write32(CxDTAEW(x) + 4, 0x502f3827);
55  }
56  } else
57  if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x16)) {
58  mchbar_write32(CxDTPEW(x), 0x02000000);
59  mchbar_write32(CxDTPEW(x) + 4, 0x0402);
60  mchbar_write32(CxDTAEW(x), 0x46061111);
61  mchbar_write32(CxDTAEW(x) + 4, 0xb579a772);
62  } else
63  if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x8)) {
64  mchbar_write32(CxDTPEW(x), 0x04070101);
65  mchbar_write32(CxDTPEW(x) + 4, 0x0501);
66  if (size == CHIP_CAP_2G) {
67  mchbar_write32(CxDTAEW(x), 0x32040e0d);
68  mchbar_write32(CxDTAEW(x) + 4, 0x55ff59ff);
69  } else
70  if (size == CHIP_CAP_1G) {
71  mchbar_write32(CxDTAEW(x), 0x3f05120a);
72  mchbar_write32(CxDTAEW(x) + 4, 0x49713a6c);
73  } else
74  if (size <= CHIP_CAP_512M) {
75  mchbar_write32(CxDTAEW(x), 0x20081808);
76  mchbar_write32(CxDTAEW(x) + 4, 0x3f23221b);
77  }
78  }
79 
80  /* also L-Shaped */
81  if (sysinfo->selected_timings.channel_mode ==
83  if (freq == MEM_CLOCK_1067MT) {
84  mchbar_write32(CxGTEW(x), 0xc8f81717);
85  } else
86  if (freq == MEM_CLOCK_800MT) {
87  mchbar_write32(CxGTEW(x), 0x96ba1717);
88  } else
89  if (freq == MEM_CLOCK_667MT) {
90  mchbar_write32(CxGTEW(x), 0x7d9b1717);
91  }
92  } else {
93  if (freq == MEM_CLOCK_1067MT) {
94  mchbar_write32(CxGTEW(x), 0x53661717);
95  } else
96  if (freq == MEM_CLOCK_800MT) {
97  mchbar_write32(CxGTEW(x), 0x886e1717);
98  } else
99  if (freq == MEM_CLOCK_667MT) {
100  mchbar_write32(CxGTEW(x), 0x38621717);
101  }
102  }
103  }
104 
105  // always?
106  mchbar_write32(CxDTC(0), 0x00004020);
107  mchbar_write32(CxDTC(1), 0x00004020);
108  mchbar_write32(CxGTC(0), 0x00304848);
109  mchbar_write32(CxGTC(1), 0x00304848);
110 
111  /* enable thermal sensors */
112  u32 tmp;
113  tmp = mchbar_read32(0x1290) & 0xfff8;
114  mchbar_write32(0x1290, tmp | 0xa4810007);
115  tmp = mchbar_read32(0x1390) & 0xfff8;
116  mchbar_write32(0x1390, tmp | 0xa4810007);
117  tmp = mchbar_read32(0x12b4) & 0xfff8;
118  mchbar_write32(0x12b4, tmp | 0xa2810007);
119  tmp = mchbar_read32(0x13b4) & 0xfff8;
120  mchbar_write32(0x13b4, tmp | 0xa2810007);
121  mchbar_write8(0x1070, 1);
122  mchbar_write8(0x1080, 6);
123  if (sysinfo->gfx_type == GMCH_PM45) {
124  mchbar_write16(0x1001, 0);
125  mchbar_write8(0x1007, 0);
126  mchbar_write32(0x1010, 0);
127  mchbar_write32(0x1014, 0);
128  mchbar_write8(0x101c, 0x98);
129  mchbar_write16(0x1041, 0x9200);
130  mchbar_write8(0x1047, 0);
131  mchbar_write32(0x1050, 0x2309);
132  mchbar_write32(0x1054, 0);
133  mchbar_write8(0x105c, 0x98);
134  } else {
135  mchbar_write16(0x1001, 0x9200);
136  mchbar_write8(0x1007, 0);
137  mchbar_write32(0x1010, 0x2309);
138  mchbar_write32(0x1014, 0);
139  mchbar_write8(0x101c, 0x98);
140  mchbar_write16(0x1041, 0);
141  mchbar_write8(0x1047, 0);
142  mchbar_write32(0x1050, 0);
143  mchbar_write32(0x1054, 0);
144  mchbar_write8(0x105c, 0x98);
145  }
146 
147  mchbar_setbits32(0x1010, 1 << 31);
148  mchbar_setbits32(0x1050, 1 << 31);
149  mchbar_setbits32(CxGTC(0), 1 << 31);
150  mchbar_setbits32(CxGTC(1), 1 << 31);
151 
152  if (sysinfo->gs45_low_power_mode) {
153  mchbar_write32(0x11b0, 0xa000083a);
154  } else if (sysinfo->gfx_type == GMCH_GM49) {
155  mchbar_write32(0x11b0, 0x2000383a);
156  mchbar_clrbits16(0x1190, 1 << 15);
157  } else if ((sysinfo->gfx_type != GMCH_PM45) &&
158  (sysinfo->gfx_type != GMCH_UNKNOWN)) {
159  mchbar_write32(0x11b0, 0xa000383a);
160  }
161 
163  case FSB_CLOCK_667MHz:
164  mchbar_write32(0x11d0, 0x0fd88000);
165  break;
166  case FSB_CLOCK_800MHz:
167  mchbar_write32(0x11d0, 0x1303c000);
168  break;
169  case FSB_CLOCK_1067MHz:
170  mchbar_write32(0x11d0, 0x194a0000);
171  break;
172  }
173  tmp = mchbar_read32(0x11d4) & ~0x1f;
174  mchbar_write32(0x11d4, tmp | 4);
175 }
static int width
Definition: bochs.c:42
#define mchbar_setbits32(addr, set)
Definition: fixed_bars.h:58
static __always_inline void mchbar_write16(const uintptr_t offset, const uint16_t value)
Definition: fixed_bars.h:31
static __always_inline void mchbar_write8(const uintptr_t offset, const uint8_t value)
Definition: fixed_bars.h:26
static __always_inline void mchbar_write32(const uintptr_t offset, const uint32_t value)
Definition: fixed_bars.h:36
#define mchbar_clrbits16(addr, clear)
Definition: fixed_bars.h:61
static __always_inline uint32_t mchbar_read32(const uintptr_t offset)
Definition: fixed_bars.h:21
#define CxDTPEW(x)
Definition: gm45.h:334
#define CxGTC(x)
Definition: gm45.h:333
#define FOR_EACH_POPULATED_CHANNEL(dimms, idx)
Definition: gm45.h:138
chip_width_t
Definition: gm45.h:62
@ CHIP_WIDTH_x8
Definition: gm45.h:64
@ CHIP_WIDTH_x16
Definition: gm45.h:65
chip_capacity_t
Definition: gm45.h:69
@ CHIP_CAP_1G
Definition: gm45.h:72
@ CHIP_CAP_512M
Definition: gm45.h:71
@ CHIP_CAP_2G
Definition: gm45.h:73
#define CxDTC(x)
Definition: gm45.h:336
#define CxDTAEW(x)
Definition: gm45.h:335
@ FSB_CLOCK_800MHz
Definition: gm45.h:10
@ FSB_CLOCK_667MHz
Definition: gm45.h:11
@ FSB_CLOCK_1067MHz
Definition: gm45.h:9
@ GMCH_PM45
Definition: gm45.h:37
@ GMCH_UNKNOWN
Definition: gm45.h:38
@ GMCH_GM49
Definition: gm45.h:31
mem_clock_t
Definition: gm45.h:41
@ MEM_CLOCK_667MT
Definition: gm45.h:47
@ MEM_CLOCK_800MT
Definition: gm45.h:46
@ MEM_CLOCK_1067MT
Definition: gm45.h:45
#define CxGTEW(x)
Definition: gm45.h:332
@ CHANNEL_MODE_DUAL_INTERLEAVED
Definition: gm45.h:59
int x
Definition: edid.c:994
void raminit_thermal(const sysinfo_t *sysinfo)
Definition: thermal.c:10
uint32_t u32
Definition: stdint.h:51
enum chip_cap chip_capacity
Definition: raminit.h:63
Definition: dw_i2c.c:39
struct dimminfo dimms[4]
Definition: raminit.h:114
struct timings selected_timings
Definition: raminit.h:113
enum fsb_clk fsb_clock
Definition: raminit.h:46
enum mem_clk mem_clock
Definition: raminit.h:47