3 #ifndef _TEGRA210_CLK_RST_H_
4 #define _TEGRA210_CLK_RST_H_
24 u32 cop_clk_skip_plcy;
31 u32 osc_freq_det_stat;
65 u32 clk_src_spdif_out;
101 u32 clk_src_vi_sensor;
149 u32 ccplex_pg_sm_ovrd;
150 u32 rst_cpu_cmplx_set;
151 u32 rst_cpu_cmplx_clr;
152 u32 clk_cpu_cmplx_set;
153 u32 clk_cpu_cmplx_clr;
165 u32 cpu_softrst_ctrl;
166 u32 cpu_softrst_ctrl1;
167 u32 cpu_softrst_ctrl2;
182 u32 clk_src_hda2codec_2x;
184 u32 clk_src_extperiph1;
185 u32 clk_src_extperiph2;
186 u32 clk_src_extperiph3;
187 u32 clk_src_nand_speed;
188 u32 clk_src_i2c_slow;
193 u32 clk_src_sata_oob;
205 u32 rst_cpug_cmplx_set;
206 u32 rst_cpug_cmplx_clr;
207 u32 rst_cpulp_cmplx_set;
208 u32 rst_cpulp_cmplx_clr;
209 u32 clk_cpug_cmplx_set;
210 u32 clk_cpug_cmplx_clr;
211 u32 clk_cpulp_cmplx_set;
212 u32 clk_cpulp_cmplx_clr;
213 u32 cpu_cmplx_status;
224 u32 prog_audio_dly_clk;
225 u32 audio_sync_clk_i2s0;
226 u32 audio_sync_clk_i2s1;
227 u32 audio_sync_clk_i2s2;
228 u32 audio_sync_clk_i2s3;
229 u32 audio_sync_clk_i2s4;
230 u32 audio_sync_clk_spdif;
254 u32 utmipll_hw_pwrdn_cfg0;
255 u32 pllu_hw_pwrdn_cfg0;
261 u32 pllx_hw_ctrl_cfg;
262 u32 pllx_sw_ramp_cfg;
263 u32 pllx_hw_ctrl_status;
265 u32 super_gr3d_clk_div;
274 u32 clk_src_xusb_core_host;
275 u32 clk_src_xusb_falcon;
277 u32 clk_src_xusb_core_dev;
285 u32 clk_src_dvfs_ref;
286 u32 clk_src_dvfs_soc;
287 u32 clk_src_traceclkin;
290 u32 clk_src_emc_latency;
291 u32 clk_src_soc_therm;
303 #define CLK_RST_REG(field_) \
304 (&(((struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE)->field_))
307 #define DEV_CONFIG_BLOCKS 7
309 #define TEGRA_DEV_L 0
310 #define TEGRA_DEV_H 1
311 #define TEGRA_DEV_U 2
312 #define TEGRA_DEV_V 0
313 #define TEGRA_DEV_W 1
315 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
318 #define CLK_ENB_CPU (1 << 0)
319 #define SWR_TRIG_SYS_RST (1 << 2)
320 #define SWR_CSITE_RST (1 << 9)
321 #define CLK_ENB_CSITE (1 << 9)
322 #define CLK_ENB_EMC_DLL (1 << 14)
325 #define CCLK_BURST_POLICY_VAL 0x20008888
327 #define CLK_M_DIVISOR_MASK (0x3 << 2)
328 #define CLK_M_DIVISOR_BY_2 (1 << 2)
331 #define SUPER_CDIV_ENB_ENABLE (1 << 31)
334 #define EN_PPSB_STOPCLK (1 << 0)
337 #define CPU3_CLK_STP_SHIFT 11
338 #define CPU2_CLK_STP_SHIFT 10
339 #define CPU1_CLK_STP_SHIFT 9
340 #define CPU0_CLK_STP_SHIFT 8
341 #define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
344 #define OSC_FREQ_SHIFT 28
345 #define OSC_FREQ_MASK (0xf << OSC_FREQ_SHIFT)
346 #define OSC_PREDIV_SHIFT 26
347 #define OSC_PREDIV_MASK (0x3 << OSC_PREDIV_SHIFT)
348 #define OSC_XOFS_SHIFT 4
349 #define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
350 #define OSC_DRIVE_STRENGTH 7
351 #define OSC_XOBP (1 << 1)
352 #define OSC_XOE (1 << 0)
365 #define PLL_BASE_BYPASS (1U << 31)
366 #define PLL_BASE_ENABLE (1U << 30)
367 #define PLL_BASE_REF_DIS (1U << 29)
368 #define PLL_BASE_OVRRIDE (1U << 28)
369 #define PLL_BASE_LOCK (1U << 27)
370 #define PLLC_BASE_LOCK (1U << 26)
372 #define PLL_BASE_DIVP_SHIFT 20
373 #define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT)
375 #define PLL_BASE_DIVN_SHIFT 8
376 #define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT)
378 #define PLL_BASE_DIVM_SHIFT 0
379 #define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT)
382 #define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT)
383 #define PLLM_BASE_DIVP_MASK (0x1fU << PLL_BASE_DIVP_SHIFT)
384 #define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT)
385 #define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT)
388 #define PLLC_MISC_RESET (1U << 30)
389 #define PLLC_MISC_1_IDDQ (1U << 27)
390 #define PLLD_N_SHIFT 11
391 #define PLLD_M_SHIFT 0
392 #define PLLD_P_SHIFT 20
393 #define PLLD_MISC1_SETUP 0x20
394 #define PLLD_MISC_EN_SDM (1 << 16)
395 #define PLLD_MISC_SDM_DIN 0x9aa
398 #define PLLM_MISC1_SETUP_SHIFT 0
399 #define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28
400 #define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29
401 #define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30
402 #define PLLM_MISC2_KCP_SHIFT 1
403 #define PLLM_MISC2_KVCO_SHIFT 0
404 #define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0)
405 #define PLLM_EN_LCKDET (1 << 4)
408 #define PLLU_MISC_IDDQ (1U << 31)
411 #define UTMIP_CFG0_PLL_MDIV_SHIFT (8)
412 #define UTMIP_CFG0_PLL_NDIV_SHIFT (16)
413 #define UTMIP_CFG1_XTAL_FREQ_COUNT_SHIFT (0)
414 #define UTMIP_CFG1_FORCE_PLL_ACTIVE_POWERDOWN_DISABLE (0 << 12)
415 #define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERDOWN_DISABLE (0 << 14)
416 #define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERUP_ENABLE (1 << 15)
417 #define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE (1 << 16)
418 #define UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT (27)
419 #define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE (0 << 0)
420 #define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE (1 << 1)
421 #define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE (0 << 2)
422 #define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE (1 << 3)
423 #define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE (0 << 4)
424 #define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE (1 << 5)
425 #define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE (0 << 24)
426 #define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE (1 << 25)
427 #define UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT (6)
428 #define UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT (18)
429 #define UTMIP_CFG2_PHY_XTAL_CLOCKEN (1U << 30)
433 #define PLL_BASE_DIV_MASK (0xffffff)
436 #define PLL_OUT_RSTN (1 << 0)
437 #define PLL_OUT_CLKEN (1 << 1)
438 #define PLL_OUT_OVR (1 << 2)
440 #define PLL_OUT_RATIO_SHIFT 8
441 #define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
443 #define PLL_OUT1_SHIFT 0
444 #define PLL_OUT2_SHIFT 16
445 #define PLL_OUT3_SHIFT 0
446 #define PLL_OUT4_SHIFT 16
449 #define PLLDPD2_MISC_LOCK_ENABLE (1 << 30)
450 #define PLLU_MISC_LOCK_ENABLE (1 << 29)
451 #define PLLD_MISC_LOCK_ENABLE (1 << 18)
452 #define PLLD_MISC_CLK_ENABLE (1 << 21)
453 #define PLLPAXS_MISC_LOCK_ENABLE (1 << 18)
454 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
457 #define PLLX_BASE_PLLX_ENABLE (1 << 30)
460 #define PLLX_IDDQ_SHIFT 3
461 #define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
463 #define CLK_DIVISOR_MASK (0xffff)
465 #define CLK_SOURCE_SHIFT 29
466 #define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT)
468 #define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16)
469 #define EMC_2X_CLK_SRC_SHIFT 29
472 #define CLK_UART_DIV_OVERRIDE (1 << 24)
475 #define SCLK_SYS_STATE_SHIFT 28U
476 #define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
484 #define SCLK_COP_FIQ_MASK (1 << 27)
485 #define SCLK_CPU_FIQ_MASK (1 << 26)
486 #define SCLK_COP_IRQ_MASK (1 << 25)
487 #define SCLK_CPU_IRQ_MASK (1 << 24)
489 #define SCLK_FIQ_SHIFT 12
490 #define SCLK_FIQ_MASK (7 << SCLK_FIQ_SHIFT)
491 #define SCLK_IRQ_SHIFT 8
492 #define SCLK_IRQ_MASK (7 << SCLK_FIQ_SHIFT)
493 #define SCLK_RUN_SHIFT 4
494 #define SCLK_RUN_MASK (7 << SCLK_FIQ_SHIFT)
495 #define SCLK_IDLE_SHIFT 0
496 #define SCLK_IDLE_MASK (7 << SCLK_FIQ_SHIFT)
509 #define SCLK_DIV_ENB (1 << 31)
510 #define SCLK_DIVIDEND_SHIFT 8
511 #define SCLK_DIVIDEND_MASK (0xff << SCLK_DIVIDEND_SHIFT)
512 #define SCLK_DIVISOR_SHIFT 0
513 #define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT)
516 #define HCLK_DISABLE (1 << 7)
517 #define HCLK_DIVISOR_SHIFT 4
518 #define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
519 #define PCLK_DISABLE (1 << 3)
520 #define PCLK_DIVISOR_SHIFT 0
521 #define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
524 #define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff
527 #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)
530 #define SET_CLK_ENB_CPUG_ENABLE (1 << 0)
531 #define SET_CLK_ENB_CPULP_ENABLE (1 << 1)
532 #define SET_CLK_ENB_MSELECT_ENABLE (1 << 3)
535 #define PLLU_POWERDOWN (1 << 16)
536 #define PLL_ENABLE_POWERDOWN (1 << 14)
537 #define PLL_ACTIVE_POWERDOWN (1 << 12)
540 #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
541 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
542 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
597 #define TIMERUS_CNTR_1US 0x0
598 #define TIMERUS_USEC_CFG 0x4
599 #define TIMERUS_USEC_CFG_19P2_CLK_M 0x045F
u32 clk_src_uart_fst_mipi_cal
check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644)
@ CRC_RST_CPUG_CLR_NONCPU
@ CRC_RST_CPULP_CLR_CORE0
@ CRC_RST_CPULP_CLR_NONCPU
@ CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB
@ CRC_CCLK_BRST_POL_CPU_STATE_RUN
@ CRC_CCLK_BRST_POL_PLLX_OUT0