coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
chromeos.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <bootmode.h>
4 #include <boot/coreboot_tables.h>
5 #include <device/pci_ops.h>
6 #include <device/device.h>
7 
10 #include <types.h>
11 #include <vendorcode/google/chromeos/chromeos.h>
12 
13 #include "onboard.h"
14 
15 void fill_lb_gpios(struct lb_gpios *gpios)
16 {
17  const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
18  u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
19 
20  struct lb_gpio chromeos_gpios[] = {
21  /* Lid switch GPIO active high (open). */
22  {GPIO_LID, ACTIVE_HIGH, get_lid_switch(), "lid"},
23 
24  /* Power Button */
25  {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
26 
27  /* Did we load the VGA Option ROM? */
28  /* -1 indicates that this is a pseudo GPIO */
29  {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
30  };
31  lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
32 }
33 
34 int get_lid_switch(void)
35 {
36  return get_gpio(GPIO_LID);
37 }
38 
40 {
41  return !get_gpio(GPIO_SPI_WP);
42 }
43 
45 {
46  return !get_gpio(GPIO_REC_MODE);
47 }
48 
49 static const struct cros_gpio cros_gpios[] = {
50  CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
51  CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
52 };
54 
56 {
57  /* Do not have a Chrome EC involved in entering recovery mode;
58  Always return trusted. */
59  return 1;
60 }
void fill_lb_gpios(struct lb_gpios *gpios)
Definition: chromeos.c:9
int get_write_protect_state(void)
Only used if CONFIG(CHROMEOS) is set.
Definition: chromeos.c:15
int gfx_get_init_done(void)
Definition: bootmode.c:10
#define ARRAY_SIZE(a)
Definition: helpers.h:12
DECLARE_CROS_GPIOS(cros_gpios)
int get_ec_is_trusted(void)
Definition: chromeos.c:25
int get_recovery_mode_switch(void)
HACK: Use Fn-Key as recovery mode switch.
Definition: chromeos.c:29
#define GPIO_SPI_WP
Definition: onboard.h:23
#define GPIO_REC_MODE
Definition: onboard.h:20
int get_lid_switch(void)
Definition: chromeos.c:37
#define ACTIVE_HIGH
Definition: chromeos.c:18
#define ACTIVE_LOW
Definition: chromeos.c:17
static const struct cros_gpio cros_gpios[]
Definition: chromeos.c:49
#define GPIO_LID
Definition: chromeos.c:12
int get_gpio(int community_base, int pad0_offset)
Definition: gpio_support.c:148
void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count)
static __always_inline uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
Definition: pci_io_cfg.h:92
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
u32 pci_devfn_t
Definition: pci_type.h:8
#define CROS_GPIO_DEVICE_NAME
Definition: gpio.h:14
#define GEN_PMCON_1
Definition: lpc.h:56
uint16_t u16
Definition: stdint.h:48