coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
finalize.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <bootstate.h>
5 #include <console/console.h>
6 #include <device/pci_ops.h>
7 #include <soc/pch.h>
8 #include <soc/pci_devs.h>
9 #include <soc/systemagent.h>
10 
11 /*
12  * 16.6 System Agent Configuration Locking
13  * "5th Generation Intel Core Processor Family BIOS Specification"
14  * Document Number 535094
15  * Revision 2.2.0, August 2014
16  *
17  * To ease reading, first lock PCI registers, then MCHBAR registers.
18  * Write the MC Lock register first, since more than one bit gets set.
19  */
21 {
22  struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT);
23 
24  pci_or_config16(host_bridge, GGC, 1 << 0);
25  pci_or_config32(host_bridge, DPR, 1 << 0);
26  pci_or_config32(host_bridge, MESEG_LIMIT, 1 << 10);
27  pci_or_config32(host_bridge, REMAPBASE, 1 << 0);
28  pci_or_config32(host_bridge, REMAPLIMIT, 1 << 0);
29  pci_or_config32(host_bridge, TOM, 1 << 0);
30  pci_or_config32(host_bridge, TOUUD, 1 << 0);
31  pci_or_config32(host_bridge, BDSM, 1 << 0);
32  pci_or_config32(host_bridge, BGSM, 1 << 0);
33  pci_or_config32(host_bridge, TSEG, 1 << 0);
34  pci_or_config32(host_bridge, TOLUD, 1 << 0);
35 
36  mchbar_setbits32(0x50fc, 0x8f); /* MC */
37  mchbar_setbits32(0x5500, 1 << 0); /* PAVP */
38  mchbar_setbits32(0x5880, 1 << 5); /* DDR PTM */
39  mchbar_setbits32(0x7000, 1 << 31);
40  mchbar_setbits32(0x77fc, 1 << 0);
41  mchbar_setbits32(0x7ffc, 1 << 0);
42  mchbar_setbits32(0x6800, 1 << 31);
43  mchbar_setbits32(0x6020, 1 << 0); /* UMA GFX */
44  mchbar_setbits32(0x63fc, 1 << 0); /* VTDTRK */
45 
46  /* Read+write the following */
47  mchbar_setbits32(0x6030, 0);
48  mchbar_setbits32(0x6034, 0);
49  mchbar_setbits32(0x6008, 0);
50 }
51 
52 static void broadwell_finalize(void *unused)
53 {
54  printk(BIOS_DEBUG, "Finalizing chipset.\n");
55 
57 
59 
60  /* Indicate finalize step with post code */
62 }
63 
@ BS_PAYLOAD_LOAD
Definition: bootstate.h:88
@ BS_OS_RESUME
Definition: bootstate.h:86
@ BS_ON_ENTRY
Definition: bootstate.h:95
@ BS_ON_EXIT
Definition: bootstate.h:96
#define printk(level,...)
Definition: stdlib.h:16
DEVTREE_CONST struct device * pcidev_path_on_root(pci_devfn_t devfn)
Definition: device_const.c:255
#define REMAPLIMIT
Definition: e7505.h:36
#define REMAPBASE
Definition: e7505.h:35
#define mchbar_setbits32(addr, set)
Definition: fixed_bars.h:58
#define GGC
Definition: host_bridge.h:9
#define MESEG_LIMIT
Definition: host_bridge.h:36
#define TOLUD
Definition: host_bridge.h:61
#define TOUUD
Definition: host_bridge.h:57
#define TSEG
Definition: host_bridge.h:60
#define BDSM
Definition: host_bridge.h:58
#define TOM
Definition: host_bridge.h:56
#define DPR
Definition: host_bridge.h:27
#define BGSM
Definition: host_bridge.h:59
static __always_inline void pci_or_config32(const struct device *dev, u16 reg, u32 ormask)
Definition: pci_ops.h:191
static __always_inline void pci_or_config16(const struct device *dev, u16 reg, u16 ormask)
Definition: pci_ops.h:180
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define post_code(value)
Definition: post_code.h:12
#define POST_OS_BOOT
Final code before OS boots.
Definition: post_codes.h:414
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL)
#define SA_DEVFN_ROOT
Definition: pci_devs.h:23
static void broadwell_finalize(void *unused)
Definition: finalize.c:52
static void broadwell_systemagent_finalize(void)
Definition: finalize.c:20
void broadwell_pch_finalize(void)
Definition: finalize.c:12
#define NULL
Definition: stddef.h:19
Definition: device.h:107