coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <baseboard/gpio.h>
4
#include <baseboard/variants.h>
5
#include <
commonlib/helpers.h
>
6
7
static
const
struct
pad_config
gpio_table
[] = {
8
/* A16 : SD_OC_ODL */
9
PAD_CFG_GPI
(
GPP_A16
,
NONE
, DEEP),
10
/* A18 : LAN_PE_ISOLATE_ODL */
11
PAD_CFG_GPO
(
GPP_A18
, 1, DEEP),
12
/* A19 : PCH_PCON0_PDB_ODL */
13
PAD_CFG_GPO
(
GPP_A19
, 1, DEEP),
14
/* A20 : LAN_I350_WAKE# */
15
PAD_CFG_GPI_IRQ_WAKE(
GPP_A20
,
NONE
, DEEP, LEVEL, INVERT),
16
/* A23 : M2_WLAN_INT_ODL */
17
PAD_CFG_GPI_APIC
(
GPP_A23
,
NONE
, PLTRST, LEVEL, INVERT),
18
19
/* B5 : LAN_CLKREQ_ODL */
20
PAD_CFG_NF
(
GPP_B5
,
NONE
, DEEP, NF1),
21
/* B6 : M2_SSD_CLKREQ_ODL */
22
PAD_CFG_NF
(
GPP_B6
,
NONE
, DEEP, NF1),
23
/* B7 : M2_TPU0_CLKREQ_ODL */
24
PAD_CFG_NF
(
GPP_B7
,
NONE
, DEEP, NF1),
25
/* B8 : CLK_PCIE_REQ3 (not connected) */
26
PAD_NC
(
GPP_B8
,
NONE
),
27
/* B9 : M2_TPU1_CLKREQ_ODL */
28
PAD_CFG_NF
(
GPP_B9
,
NONE
, DEEP, NF1),
29
/* B10 : M2_WLAN_CLKREQ_ODL */
30
PAD_CFG_NF
(
GPP_B10
,
NONE
, DEEP, NF1),
31
32
/* C0 : SMBCLK */
33
PAD_CFG_NF
(
GPP_C0
,
NONE
, DEEP, NF1),
34
/* C1 : SMBDATA */
35
PAD_CFG_NF
(
GPP_C1
,
NONE
, DEEP, NF1),
36
/* C3 : PCH_MBCLK1_R (i350) */
37
PAD_CFG_NF
(
GPP_C3
,
NONE
, DEEP, NF1),
38
/* C4 : PCH_MBDAT1_R (i350) */
39
PAD_CFG_NF
(
GPP_C4
,
NONE
, DEEP, NF1),
40
/* C6 : M2_WLAN_WAKE_ODL */
41
PAD_CFG_GPI_SCI_LOW
(
GPP_C6
,
NONE
, DEEP, EDGE_SINGLE),
42
/* C7 : LAN_WAKE_ODL */
43
PAD_CFG_GPI_SCI_LOW
(
GPP_C7
,
NONE
, DEEP, EDGE_SINGLE),
44
/* C10 : PCH_PCON_RST_ODL */
45
PAD_CFG_GPO
(
GPP_C10
, 1, DEEP),
46
/* C11 : PCH_PCON1_PDB_ODL */
47
PAD_CFG_GPO
(
GPP_C11
, 1, DEEP),
48
/* C12 : PCH_UART1_RX_ADB_TX */
49
PAD_CFG_NF
(
GPP_C12
,
NONE
, DEEP, NF1),
50
/* C13 : PCH_UART1_TX_ADB_RX */
51
PAD_CFG_NF
(
GPP_C13
,
NONE
, DEEP, NF1),
52
/* C15 : WLAN_OFF_L */
53
PAD_CFG_GPO
(
GPP_C15
, 1, DEEP),
54
/* C16 : PCH_I2C_RFU_SDA (NC) */
55
PAD_NC
(
GPP_C16
,
NONE
),
56
/* C17 : PCH_I2C_RFU_SCL (NC) */
57
PAD_NC
(
GPP_C17
,
NONE
),
58
/* C18 : EC_I2C_HDMI_RE_SCL */
59
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
60
/* C19 : EC_12C_HDMI_RE_SDA */
61
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
62
63
/* D1 : REC_MODE */
64
PAD_CFG_GPO
(
GPP_D1
, 1, DEEP),
65
/* D2 : DEV_MODE_CTRL */
66
PAD_CFG_GPO
(
GPP_D2
, 1, DEEP),
67
/* D3 : BOOT_IND */
68
PAD_CFG_GPI
(
GPP_D3
,
NONE
, DEEP),
69
/* D14 : EC_PCH_INT_L */
70
PAD_CFG_GPI_APIC
(
GPP_D14
,
NONE
, PLTRST, LEVEL, INVERT),
71
/* D21 : BOOT_SEL_N */
72
PAD_CFG_GPO
(
GPP_D21
, 1, DEEP),
73
/* D22 : QSPI_MR_N */
74
PAD_CFG_GPO
(
GPP_D22
, 1, DEEP),
75
/* D23 : Not connected */
76
PAD_NC
(
GPP_D23
,
NONE
),
77
78
/* E2 : Not connected */
79
PAD_NC
(
GPP_E2
,
NONE
),
80
/* E3 : TPU_BOOT_DELAY_PIN40 */
81
PAD_CFG_GPO
(
GPP_E3
, 1, DEEP),
82
/* E7 : TPU_BOOT_DELAY_PIN42 */
83
PAD_CFG_GPO
(
GPP_E7
, 1, DEEP),
84
/* E9 : PU 10K to PP3300_SOC_A */
85
PAD_NC
(
GPP_E9
,
NONE
),
86
/* E10 : USB_A1_OC_ODL */
87
PAD_CFG_NF
(
GPP_E10
,
NONE
, DEEP, NF1),
88
/* E11 : PU 10K to PP3300_SOC_A */
89
PAD_NC
(
GPP_E11
,
NONE
),
90
/* E12 : PU 10K to PP3300_SOC_A */
91
PAD_NC
(
GPP_E12
,
NONE
),
92
/* E15 : PCH_TYPEC_UPFB */
93
PAD_CFG_GPI
(
GPP_E15
,
NONE
, DEEP),
94
95
/* H0 : Not connected */
96
PAD_NC
(
GPP_H0
,
NONE
),
97
/* H4 : PCH_I2C_PCON_SDA */
98
PAD_CFG_NF
(
GPP_H4
,
NONE
, DEEP, NF1),
99
/* H5 : PCH_I2C_PCON_SCL */
100
PAD_CFG_NF
(
GPP_H5
,
NONE
, DEEP, NF1),
101
/* H6 : PCH_I2C_TPU_SDA */
102
PAD_CFG_NF
(
GPP_H6
,
NONE
, DEEP, NF1),
103
/* H7 : PCH_I2C_TPU_SCL */
104
PAD_CFG_NF
(
GPP_H7
,
NONE
, DEEP, NF1),
105
/* H8 : Not connected */
106
PAD_NC
(
GPP_H8
,
NONE
),
107
/* H9 : Not connected */
108
PAD_NC
(
GPP_H9
,
NONE
),
109
/* H22 : PWM_PP3300_BIOZZER */
110
PAD_CFG_GPO
(
GPP_H22
, 0, DEEP),
111
};
112
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const
struct
pad_config
*
override_gpio_table
(
size_t
*num)
114
{
115
*num =
ARRAY_SIZE
(
gpio_table
);
116
return
gpio_table
;
117
}
118
119
/* Early pad configuration in bootblock */
120
static
const
struct
pad_config
early_gpio_table
[] = {
121
/* B14 : GPP_B14_STRAP */
122
PAD_NC
(
GPP_B14
,
NONE
),
123
/* B22 : GPP_B22_STRAP */
124
PAD_NC
(
GPP_B22
,
NONE
),
125
/* E19 : GPP_E19_STRAP */
126
PAD_NC
(
GPP_E19
,
NONE
),
127
/* E21 : GPP_E21_STRAP */
128
PAD_NC
(
GPP_E21
,
NONE
),
129
/* B15 : H1_SLAVE_SPI_CS_L */
130
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
131
/* B16 : H1_SLAVE_SPI_CLK */
132
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
133
/* B17 : H1_SLAVE_SPI_MISO_R */
134
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
135
/* B18 : H1_SLAVE_SPI_MOSI_R */
136
PAD_CFG_NF
(
GPP_B18
,
NONE
, DEEP, NF1),
137
/* C14 : BT_DISABLE_L */
138
PAD_CFG_GPO
(
GPP_C14
, 0, DEEP),
139
/* C20 : PCH_WP_OD */
140
PAD_CFG_GPI
(
GPP_C20
,
NONE
, DEEP),
141
/* C21 : H1_PCH_INT_ODL */
142
PAD_CFG_GPI_APIC
(
GPP_C21
,
NONE
, PLTRST, LEVEL, INVERT),
143
/* C22 : EC_IN_RW_OD */
144
PAD_CFG_GPI
(
GPP_C22
,
NONE
, DEEP),
145
/* C23 : WLAN_PE_RST# */
146
PAD_CFG_GPO
(
GPP_C23
, 1, DEEP),
147
/* E1 : M2_SSD_PEDET */
148
PAD_CFG_NF
(
GPP_E1
,
NONE
, DEEP, NF1),
149
/* E5 : SATA_DEVSLP1 */
150
PAD_CFG_NF
(
GPP_E5
,
NONE
, PLTRST, NF1),
151
};
152
153
const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
154
{
155
*num =
ARRAY_SIZE
(
early_gpio_table
);
156
return
early_gpio_table
;
157
}
GPP_H22
#define GPP_H22
Definition:
gpio_soc_defs.h:238
GPP_C15
#define GPP_C15
Definition:
gpio_soc_defs.h:552
GPP_B6
#define GPP_B6
Definition:
gpio_soc_defs.h:59
GPP_D1
#define GPP_D1
Definition:
gpio_soc_defs.h:253
GPP_E3
#define GPP_E3
Definition:
gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_C12
#define GPP_C12
Definition:
gpio_soc_defs.h:549
GPP_D14
#define GPP_D14
Definition:
gpio_soc_defs.h:266
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_D2
#define GPP_D2
Definition:
gpio_soc_defs.h:254
GPP_H6
#define GPP_H6
Definition:
gpio_soc_defs.h:222
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPP_H9
#define GPP_H9
Definition:
gpio_soc_defs.h:225
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_H7
#define GPP_H7
Definition:
gpio_soc_defs.h:223
GPP_C11
#define GPP_C11
Definition:
gpio_soc_defs.h:548
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_C13
#define GPP_C13
Definition:
gpio_soc_defs.h:550
GPP_E9
#define GPP_E9
Definition:
gpio_soc_defs.h:637
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_E5
#define GPP_E5
Definition:
gpio_soc_defs.h:633
GPP_B8
#define GPP_B8
Definition:
gpio_soc_defs.h:61
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_A20
#define GPP_A20
Definition:
gpio_soc_defs.h:139
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_C6
#define GPP_C6
Definition:
gpio_soc_defs.h:543
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_E19
#define GPP_E19
Definition:
gpio_soc_defs.h:647
GPP_H0
#define GPP_H0
Definition:
gpio_soc_defs.h:215
GPP_H5
#define GPP_H5
Definition:
gpio_soc_defs.h:221
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPP_B14
#define GPP_B14
Definition:
gpio_soc_defs.h:67
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_B5
#define GPP_B5
Definition:
gpio_soc_defs.h:58
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_E10
#define GPP_E10
Definition:
gpio_soc_defs.h:638
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_C1
#define GPP_C1
Definition:
gpio_soc_defs.h:538
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPP_E21
#define GPP_E21
Definition:
gpio_soc_defs.h:649
GPP_C3
#define GPP_C3
Definition:
gpio_soc_defs.h:540
GPP_E12
#define GPP_E12
Definition:
gpio_soc_defs.h:640
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_H8
#define GPP_H8
Definition:
gpio_soc_defs.h:224
GPP_H4
#define GPP_H4
Definition:
gpio_soc_defs.h:220
GPP_B7
#define GPP_B7
Definition:
gpio_soc_defs.h:60
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
GPP_D3
#define GPP_D3
Definition:
gpio_soc_defs.h:255
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
GPP_D23
#define GPP_D23
Definition:
gpio_soc_defs.h:133
GPP_D22
#define GPP_D22
Definition:
gpio_soc_defs.h:132
GPP_D21
#define GPP_D21
Definition:
gpio_soc_defs.h:131
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
override_gpio_table
const struct pad_config * override_gpio_table(size_t *num)
Definition:
gpio.c:124
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.c:7
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:120
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI
#define PAD_CFG_GPI(pad, pull, rst)
Definition:
gpio_defs.h:284
PAD_CFG_GPI_SCI_LOW
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig)
Definition:
gpio_defs.h:452
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
pad_config
Definition:
gpio.h:75
src
mainboard
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variants
moonbuggy
gpio.c
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