coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <
device/pci_ids.h
>
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const
struct
cpu_power_limits
limits
[] = {
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/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
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/* All values are for baseline config as per bug:191906315 comment #10 */
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{
PCI_DID_INTEL_ADL_P_ID_7
, 15, 3000, 15000, 39000, 39000, 100000 },
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{
PCI_DID_INTEL_ADL_P_ID_6
, 15, 3000, 15000, 39000, 39000, 100000 },
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{
PCI_DID_INTEL_ADL_P_ID_5
, 28, 4000, 28000, 43000, 43000, 105000 },
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{
PCI_DID_INTEL_ADL_P_ID_3
, 28, 4000, 28000, 43000, 43000, 105000 },
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{
PCI_DID_INTEL_ADL_P_ID_3
, 45, 5000, 45000, 80000, 80000, 159000 },
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};
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void
variant_devtree_update
(
void
)
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{
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size_t
total_entries =
ARRAY_SIZE
(
limits
);
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variant_update_power_limits
(
limits
, total_entries);
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}
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
variant_update_power_limits
void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
Definition:
ramstage.c:51
variant_devtree_update
void variant_devtree_update(void)
Definition:
ramstage.c:63
limits
const struct cpu_power_limits limits[]
Definition:
ramstage.c:11
pci_ids.h
PCI_DID_INTEL_ADL_P_ID_7
#define PCI_DID_INTEL_ADL_P_ID_7
Definition:
pci_ids.h:4069
PCI_DID_INTEL_ADL_P_ID_3
#define PCI_DID_INTEL_ADL_P_ID_3
Definition:
pci_ids.h:4065
PCI_DID_INTEL_ADL_P_ID_5
#define PCI_DID_INTEL_ADL_P_ID_5
Definition:
pci_ids.h:4067
PCI_DID_INTEL_ADL_P_ID_6
#define PCI_DID_INTEL_ADL_P_ID_6
Definition:
pci_ids.h:4068
cpu_power_limits
Definition:
variants.h:39
src
mainboard
google
brya
variants
brya4es
ramstage.c
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