coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/variants.h>
4 #include <device/pci_ids.h>
5 
6 const struct cpu_power_limits limits[] = {
7  /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
8  /* All values are for baseline config as per bug:191906315 comment #10 */
9  { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
10  { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
11  { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
12  { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
13  { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
14 };
15 
17 {
18  size_t total_entries = ARRAY_SIZE(limits);
19  variant_update_power_limits(limits, total_entries);
20 }
#define ARRAY_SIZE(a)
Definition: helpers.h:12
void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
Definition: ramstage.c:51
void variant_devtree_update(void)
Definition: ramstage.c:63
const struct cpu_power_limits limits[]
Definition: ramstage.c:11
#define PCI_DID_INTEL_ADL_P_ID_7
Definition: pci_ids.h:4069
#define PCI_DID_INTEL_ADL_P_ID_3
Definition: pci_ids.h:4065
#define PCI_DID_INTEL_ADL_P_ID_5
Definition: pci_ids.h:4067
#define PCI_DID_INTEL_ADL_P_ID_6
Definition: pci_ids.h:4068