coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#ifndef MAINBOARD_GPIO_H
4
#define MAINBOARD_GPIO_H
5
6
#include <soc/gpe.h>
7
#include <soc/gpio.h>
8
9
/* EC in RW */
10
#define GPIO_EC_IN_RW GPP_C6
11
12
/* BIOS Flash Write Protect */
13
#define GPIO_PCH_WP GPP_C23
14
15
/* Memory configuration board straps */
16
#define GPIO_MEM_CONFIG_0 GPP_C12
17
#define GPIO_MEM_CONFIG_1 GPP_C13
18
#define GPIO_MEM_CONFIG_2 GPP_C14
19
#define GPIO_MEM_CONFIG_3 GPP_C15
20
21
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
22
#define GPE_EC_WAKE GPE0_LAN_WAK
23
24
/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
25
#define GPE_WLAN_WAKE GPE0_DW0_16
26
27
/* Input device interrupt configuration */
28
#define TOUCHPAD_INT_L GPP_B3_IRQ
29
#define TOUCHSCREEN_INT_L GPP_E7_IRQ
30
#define MIC_INT_L GPP_F10_IRQ
31
32
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
33
#define EC_SCI_GPI GPE0_DW2_16
34
#define EC_SMI_GPI GPP_E15
35
36
/* Power rail control signals. */
37
#define EN_PP3300_KEPLER GPP_C11
38
#define EN_PP3300_DX_TOUCH GPP_C22
39
#define EN_PP3300_DX_EMMC GPP_D5
40
#define EN_PP1800_DX_EMMC GPP_D6
41
#define EN_PP3300_DX_CAM GPP_D12
42
43
#ifndef __ACPI__
44
/* Pad configuration in ramstage. */
45
static
const
struct
pad_config
gpio_table
[] = {
46
/* RCIN# */
PAD_CFG_NF
(
GPP_A0
,
NONE
, DEEP, NF1),
47
/* LAD0 */
PAD_CFG_NF
(
GPP_A1
, UP_20K, DEEP, NF1),
48
/* LAD1 */
PAD_CFG_NF
(
GPP_A2
, UP_20K, DEEP, NF1),
49
/* LAD2 */
PAD_CFG_NF
(
GPP_A3
, UP_20K, DEEP, NF1),
50
/* LAD3 */
PAD_CFG_NF
(
GPP_A4
, UP_20K, DEEP, NF1),
51
/* LFRAME# */
PAD_CFG_NF
(
GPP_A5
,
NONE
, DEEP, NF1),
52
/* SERIRQ */
PAD_CFG_NF
(
GPP_A6
,
NONE
, DEEP, NF1),
53
/* PIRQA# */
/* GPP_A7 */
54
/* CLKRUN# */
PAD_CFG_NF
(
GPP_A8
,
NONE
, DEEP, NF1),
55
/* CLKOUT_LPC0 */
PAD_CFG_NF
(
GPP_A9
,
NONE
, DEEP, NF1),
56
/* CLKOUT_LPC1 */
/* GPP_A10 */
57
/* PME# */
/* GPP_A11 */
58
/* BM_BUSY# */
/* GPP_A12 */
59
/* SUSWARN# */
PAD_CFG_NF
(
GPP_A13
,
NONE
, DEEP, NF1),
60
/* SUS_STAT# */
PAD_CFG_NF
(
GPP_A14
,
NONE
, DEEP, NF1),
61
/* SUSACK# */
PAD_CFG_NF
(
GPP_A15
,
NONE
, DEEP, NF1),
62
/* SD_1P8_SEL */
PAD_CFG_NF
(
GPP_A16
,
NONE
, DEEP, NF1),
63
/* SD_PWR_EN# */
PAD_CFG_NF
(
GPP_A17
,
NONE
, DEEP, NF1),
64
/* ISH_GP0 */
/* GPP_A18 */
65
/* ISH_GP1 */
/* GPP_A19 */
66
/* ISH_GP2 */
/* GPP_A20 */
67
/* ISH_GP3 */
/* GPP_A21 */
68
/* ISH_GP4 */
/* GPP_A22 */
69
/* ISH_GP5 */
/* GPP_A23 */
70
/* CORE_VID0 */
/* GPP_B0 */
71
/* CORE_VID1 */
/* GPP_B1 */
72
/* VRALERT# */
/* GPP_B2 */
73
/* CPU_GP2 */
PAD_CFG_GPI_APIC_HIGH
(
GPP_B3
,
NONE
, DEEP),
/* TRACKPAD */
74
/* CPU_GP3 */
/* GPP_B4 */
75
/* SRCCLKREQ0# */
/* GPP_B5 */
76
/* SRCCLKREQ1# */
PAD_CFG_NF
(
GPP_B6
,
NONE
, DEEP, NF1),
/* WLAN */
77
/* SRCCLKREQ2# */
PAD_CFG_NF
(
GPP_B7
,
NONE
, DEEP, NF1),
/* KEPLER */
78
/* SRCCLKREQ3# */
/* GPP_B8 */
79
/* SRCCLKREQ4# */
/* GPP_B9 */
80
/* SRCCLKREQ5# */
/* GPP_B10 */
81
/* EXT_PWR_GATE# */
PAD_CFG_NF
(
GPP_B11
,
NONE
, DEEP, NF1),
82
/* SLP_S0# */
PAD_CFG_NF
(
GPP_B12
,
NONE
, DEEP, NF1),
83
/* PLTRST# */
PAD_CFG_NF
(
GPP_B13
,
NONE
, DEEP, NF1),
84
/* SPKR */
/* GPP_B14 */
85
/* GSPI0_CS# */
/* GPP_B15 */
86
/* GSPI0_CLK */
PAD_CFG_GPI_SCI
(
GPP_B16
,
NONE
, DEEP, EDGE_SINGLE, INVERT),
/* WLAN WAKE */
87
/* GSPI0_MISO */
/* GPP_B17 */
88
/* GSPI0_MOSI */
/* GPP_B18 */
89
/* GSPI1_CS# */
/* GPP_B19 */
90
/* GSPI1_CLK */
/* GPP_B20 */
91
/* GSPI1_MISO */
/* GPP_B21 */
92
/* GSPI1_MOSI */
/* GPP_B22 */
93
/* SM1ALERT# */
PAD_CFG_GPO
(
GPP_B23
, 0, DEEP),
94
/* SMBCLK */
PAD_CFG_NF
(
GPP_C0
,
NONE
, DEEP, NF1),
/* XDP */
95
/* SMBDATA */
PAD_CFG_NF
(
GPP_C1
,
NONE
, DEEP, NF1),
/* XDP */
96
/* SMBALERT# */
/* GPP_C2 */
97
/* SML0CLK */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C3
,
NONE
, DEEP),
98
/* SML0DATA */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C4
,
NONE
, DEEP),
99
/* SML0ALERT# */
PAD_CFG_GPO
(
GPP_C5
, 0, DEEP),
100
/* SM1CLK */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C6
, UP_20K,
101
DEEP),
/* EC_IN_RW */
102
/* SM1DATA */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C7
,
NONE
, DEEP),
103
/* UART0_RXD */
/* GPP_C8 */
104
/* UART0_TXD */
/* GPP_C9 */
105
/* UART0_RTS# */
/* GPP_C10 */
106
/* UART0_CTS# */
PAD_CFG_GPO
(
GPP_C11
, 0, DEEP),
/* EN_PP3300_KEPLER */
107
/* UART1_RXD */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C12
,
NONE
,
108
DEEP),
/* MEM_CONFIG[0] */
109
/* UART1_TXD */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C13
,
NONE
,
110
DEEP),
/* MEM_CONFIG[1] */
111
/* UART1_RTS# */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C14
,
NONE
,
112
DEEP),
/* MEM_CONFIG[2] */
113
/* UART1_CTS# */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C15
,
NONE
,
114
DEEP),
/* MEM_CONFIG[3] */
115
/* I2C0_SDA */
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
/* TOUCHSCREEN */
116
/* I2C0_SCL */
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
/* TOUCHSCREEN */
117
/* I2C1_SDA */
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
/* TRACKPAD */
118
/* I2C1_SCL */
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
/* TRACKPAD */
119
/* UART2_RXD */
PAD_CFG_NF
(
GPP_C20
,
NONE
, DEEP, NF1),
/* SERVO */
120
/* UART2_TXD */
PAD_CFG_NF
(
GPP_C21
,
NONE
, DEEP, NF1),
/* SERVO */
121
/* UART2_RTS# */
PAD_CFG_GPO
(
GPP_C22
, 1, DEEP),
/* EN_PP3300_DX_TOUCH */
122
/* UART2_CTS# */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C23
, UP_20K,
123
DEEP),
/* PCH_WP */
124
/* GPP_D0 */
125
/* GPP_D1 */
126
/* GPP_D2 */
127
/* GPP_D3 */
128
/* FASHTRIG */
/* GPP_D4 */
129
/* ISH_I2C0_SDA */
PAD_CFG_GPO
(
GPP_D5
, 1, DEEP),
/* EN_PP3300_DX_EMMC */
130
/* ISH_I2C0_SCL */
PAD_CFG_GPO
(
GPP_D6
, 1, DEEP),
/* EN_PP1800_DX_EMMC */
131
/* ISH_I2C1_SDA */
/* GPP_D7 */
132
/* ISH_I2C1_SCL */
/* GPP_D8 */
133
/* GPP_D9 */
134
PAD_CFG_GPO
(
GPP_D10
, 1, DEEP),
/* USBA_1_ILIM_SEL_L */
135
PAD_CFG_GPO
(
GPP_D11
, 1, DEEP),
/* USBA_2_ILIM_SEL_L */
136
PAD_CFG_GPO
(
GPP_D12
, 1, DEEP),
/* EN_PP3300_DX_CAM */
137
/* ISH_UART0_RXD */
/* GPP_D13 */
138
/* ISH_UART0_TXD */
/* GPP_D14 */
139
/* ISH_UART0_RTS# */
/* GPP_D15 */
140
/* ISH_UART0_CTS# */
/* GPP_D16 */
141
/* DMIC_CLK1 */
PAD_CFG_NF
(
GPP_D17
,
NONE
, DEEP, NF1),
142
/* DMIC_DATA1 */
PAD_CFG_NF
(
GPP_D18
,
NONE
, DEEP, NF1),
143
/* DMIC_CLK0 */
PAD_CFG_NF
(
GPP_D19
,
NONE
, DEEP, NF1),
144
/* DMIC_DATA0 */
PAD_CFG_NF
(
GPP_D20
,
NONE
, DEEP, NF1),
145
/* GPP_D21 */
146
/* GPP_D22 */
147
/* I2S_MCLK */
PAD_CFG_NF
(
GPP_D23
,
NONE
, DEEP, NF1),
148
/* SPI_TPM_IRQ */
PAD_NC
(
GPP_E0
,
NONE
),
149
/* SATAXPCIE1 */
/* GPP_E1 */
150
/* SATAXPCIE2 */
/* GPP_E2 */
151
/* CPU_GP0 */
/* GPP_E3 */
152
/* SATA_DEVSLP0 */
/* GPP_E4 */
153
/* SATA_DEVSLP1 */
/* GPP_E5 */
154
/* SATA_DEVSLP2 */
/* GPP_E6 */
155
/* CPU_GP1 */
PAD_CFG_GPI_APIC_HIGH
(
GPP_E7
,
NONE
, DEEP),
/* TOUCHSCREEN */
156
/* SATALED# */
/* GPP_E8 */
157
/* USB2_OCO# */
PAD_CFG_NF
(
GPP_E9
,
NONE
, DEEP, NF1),
158
/* USB2_OC1# */
PAD_CFG_NF
(
GPP_E10
,
NONE
, DEEP, NF1),
159
/* USB2_OC2# */
PAD_CFG_NF
(
GPP_E11
,
NONE
, DEEP, NF1),
160
/* USB2_OC3# */
PAD_CFG_NF
(
GPP_E12
,
NONE
, DEEP, NF1),
161
/* DDPB_HPD0 */
PAD_CFG_NF
(
GPP_E13
,
NONE
, DEEP, NF1),
162
/* DDPC_HPD1 */
PAD_CFG_NF
(
GPP_E14
,
NONE
, DEEP, NF1),
163
/* DDPD_HPD2 */
PAD_CFG_GPI_SMI
(
GPP_E15
,
NONE
, DEEP, EDGE_SINGLE, INVERT),
/* EC_SMI_L */
164
/* DDPE_HPD3 */
PAD_CFG_GPI_SCI
(
GPP_E16
,
NONE
, DEEP, EDGE_SINGLE, INVERT),
/* EC_SCI_L */
165
/* EDP_HPD */
PAD_CFG_NF
(
GPP_E17
,
NONE
, DEEP, NF1),
166
/* DDPB_CTRLCLK */
/* GPP_E18 */
167
/* DDPB_CTRLDATA */
/* GPP_E19 */
168
/* DDPC_CTRLCLK */
/* GPP_E20 */
169
/* DDPC_CTRLDATA */
/* GPP_E21 */
170
/* GPP_E22 */
171
/* GPP_E23 */
172
/*
173
* The next 4 pads are for bit banging the amplifiers. They are connected
174
* together with i2s0 signals. For default behavior of i2s make these
175
* gpio inputs.
176
*/
177
/* I2S2_SCLK */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F0
,
NONE
, DEEP),
178
/* I2S2_SFRM */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F1
,
NONE
, DEEP),
179
/* I2S2_TXD */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F2
,
NONE
, DEEP),
180
/* I2S2_RXD */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F3
,
NONE
, DEEP),
181
/* I2C2_SDA */
/* GPP_F4 */
182
/* I2C2_SCL */
/* GPP_F5 */
183
/* I2C3_SDA */
/* GPP_F6 */
184
/* I2C3_SCL */
/* GPP_F7 */
185
/* I2C4_SDA */
PAD_CFG_NF_1V8(
GPP_F8
,
NONE
, DEEP, NF1),
/* Amplifiers */
186
/* I2C4_SCL */
PAD_CFG_NF_1V8(
GPP_F9
,
NONE
, DEEP, NF1),
/* Amplifiers */
187
/* I2C5_SDA */
PAD_CFG_GPI_APIC_HIGH
(
GPP_F10
,
NONE
, DEEP),
/* MIC_INT_L */
188
/* I2C5_SCL */
/* GPP_F11 */
189
/* EMMC_CMD */
PAD_CFG_NF
(
GPP_F12
,
NONE
, DEEP, NF1),
190
/* EMMC_DATA0 */
PAD_CFG_NF
(
GPP_F13
,
NONE
, DEEP, NF1),
191
/* EMMC_DATA1 */
PAD_CFG_NF
(
GPP_F14
,
NONE
, DEEP, NF1),
192
/* EMMC_DATA2 */
PAD_CFG_NF
(
GPP_F15
,
NONE
, DEEP, NF1),
193
/* EMMC_DATA3 */
PAD_CFG_NF
(
GPP_F16
,
NONE
, DEEP, NF1),
194
/* EMMC_DATA4 */
PAD_CFG_NF
(
GPP_F17
,
NONE
, DEEP, NF1),
195
/* EMMC_DATA5 */
PAD_CFG_NF
(
GPP_F18
,
NONE
, DEEP, NF1),
196
/* EMMC_DATA6 */
PAD_CFG_NF
(
GPP_F19
,
NONE
, DEEP, NF1),
197
/* EMMC_DATA7 */
PAD_CFG_NF
(
GPP_F20
,
NONE
, DEEP, NF1),
198
/* EMMC_RCLK */
PAD_CFG_NF
(
GPP_F21
,
NONE
, DEEP, NF1),
199
/* EMMC_CLK */
PAD_CFG_NF
(
GPP_F22
,
NONE
, DEEP, NF1),
200
/* GPP_F23 */
201
/* SD_CMD */
PAD_CFG_NF
(
GPP_G0
,
NONE
, DEEP, NF1),
202
/* SD_DATA0 */
PAD_CFG_NF
(
GPP_G1
,
NONE
, DEEP, NF1),
203
/* SD_DATA1 */
PAD_CFG_NF
(
GPP_G2
,
NONE
, DEEP, NF1),
204
/* SD_DATA2 */
PAD_CFG_NF
(
GPP_G3
,
NONE
, DEEP, NF1),
205
/* SD_DATA3 */
PAD_CFG_NF
(
GPP_G4
,
NONE
, DEEP, NF1),
206
/* SD_CD# */
PAD_CFG_NF
(
GPP_G5
,
NONE
, DEEP, NF1),
207
/* SD_CLK */
PAD_CFG_NF
(
GPP_G6
,
NONE
, DEEP, NF1),
208
/* SD_WP */
PAD_CFG_NF
(
GPP_G7
,
NONE
, DEEP, NF1),
209
/* BATLOW# */
/* GPD0 */
210
/* ACPRESENT */
PAD_CFG_NF
(
GPD1
,
NONE
, DEEP, NF1),
211
/* LAN_WAKE# */
PAD_CFG_NF
(
GPD2
,
NONE
, DEEP, NF1),
/* EC_PCH_WAKE_L */
212
/* PWRBTN# */
PAD_CFG_NF
(
GPD3
,
NONE
, DEEP, NF1),
213
/* SLP_S3# */
PAD_CFG_NF
(
GPD4
,
NONE
, DEEP, NF1),
214
/* SLP_S4# */
PAD_CFG_NF
(
GPD5
,
NONE
, DEEP, NF1),
215
/* SLP_A# */
PAD_CFG_NF
(
GPD6
,
NONE
, DEEP, NF1),
216
/* GPD7 */
217
/* SUSCLK */
PAD_CFG_NF
(
GPD8
,
NONE
, DEEP, NF1),
218
/* SLP_WLAN# */
/* GPD9 */
219
/* SLP_S5# */
PAD_CFG_NF
(
GPD10
,
NONE
, DEEP, NF1),
220
/* LANPHYC */
/* GPD11 */
221
};
222
223
/* Early pad configuration in bootblock */
224
static
const
struct
pad_config
early_gpio_table
[] = {
225
/* SRCCLKREQ2# */
PAD_CFG_NF
(
GPP_B7
,
NONE
, DEEP, NF1),
/* KEPLER */
226
/* UART0_CTS# */
PAD_CFG_GPO
(
GPP_C11
, 0, DEEP),
/* EN_PP3300_KEPLER */
227
/* GD_UART2_RXD */
PAD_CFG_NF
(
GPP_C20
,
NONE
, DEEP, NF1),
228
/* GD_UART2_TXD */
PAD_CFG_NF
(
GPP_C21
,
NONE
, DEEP, NF1),
229
/* SM1CLK */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C6
, UP_20K,
230
DEEP),
/* EC_IN_RW */
231
};
232
233
#endif
234
235
#endif
GPP_A4
#define GPP_A4
Definition:
gpio_soc_defs.h:123
GPP_C15
#define GPP_C15
Definition:
gpio_soc_defs.h:552
GPD3
#define GPD3
Definition:
gpio_soc_defs.h:384
GPP_B6
#define GPP_B6
Definition:
gpio_soc_defs.h:59
GPP_D10
#define GPP_D10
Definition:
gpio_soc_defs.h:262
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_F21
#define GPP_F21
Definition:
gpio_soc_defs.h:594
GPP_C12
#define GPP_C12
Definition:
gpio_soc_defs.h:549
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_F16
#define GPP_F16
Definition:
gpio_soc_defs.h:589
GPP_E0
#define GPP_E0
Definition:
gpio_soc_defs.h:628
GPP_F20
#define GPP_F20
Definition:
gpio_soc_defs.h:593
GPP_C5
#define GPP_C5
Definition:
gpio_soc_defs.h:542
GPP_A14
#define GPP_A14
Definition:
gpio_soc_defs.h:133
GPP_B12
#define GPP_B12
Definition:
gpio_soc_defs.h:65
GPP_D12
#define GPP_D12
Definition:
gpio_soc_defs.h:264
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_A5
#define GPP_A5
Definition:
gpio_soc_defs.h:124
GPP_B13
#define GPP_B13
Definition:
gpio_soc_defs.h:66
GPP_F0
#define GPP_F0
Definition:
gpio_soc_defs.h:573
GPP_D6
#define GPP_D6
Definition:
gpio_soc_defs.h:258
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPP_E13
#define GPP_E13
Definition:
gpio_soc_defs.h:641
GPP_A2
#define GPP_A2
Definition:
gpio_soc_defs.h:121
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_D11
#define GPP_D11
Definition:
gpio_soc_defs.h:263
GPP_A6
#define GPP_A6
Definition:
gpio_soc_defs.h:125
GPP_C11
#define GPP_C11
Definition:
gpio_soc_defs.h:548
GPP_D5
#define GPP_D5
Definition:
gpio_soc_defs.h:257
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_F9
#define GPP_F9
Definition:
gpio_soc_defs.h:582
GPP_C13
#define GPP_C13
Definition:
gpio_soc_defs.h:550
GPP_E14
#define GPP_E14
Definition:
gpio_soc_defs.h:642
GPP_E9
#define GPP_E9
Definition:
gpio_soc_defs.h:637
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_A0
#define GPP_A0
Definition:
gpio_soc_defs.h:119
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_F1
#define GPP_F1
Definition:
gpio_soc_defs.h:574
GPP_F17
#define GPP_F17
Definition:
gpio_soc_defs.h:590
GPP_F15
#define GPP_F15
Definition:
gpio_soc_defs.h:588
GPP_C6
#define GPP_C6
Definition:
gpio_soc_defs.h:543
GPD2
#define GPD2
Definition:
gpio_soc_defs.h:383
GPP_F10
#define GPP_F10
Definition:
gpio_soc_defs.h:583
GPP_A3
#define GPP_A3
Definition:
gpio_soc_defs.h:122
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPD1
#define GPD1
Definition:
gpio_soc_defs.h:382
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_D18
#define GPP_D18
Definition:
gpio_soc_defs.h:270
GPP_E17
#define GPP_E17
Definition:
gpio_soc_defs.h:645
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPD10
#define GPD10
Definition:
gpio_soc_defs.h:391
GPP_F14
#define GPP_F14
Definition:
gpio_soc_defs.h:587
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_A1
#define GPP_A1
Definition:
gpio_soc_defs.h:120
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_A15
#define GPP_A15
Definition:
gpio_soc_defs.h:134
GPP_A9
#define GPP_A9
Definition:
gpio_soc_defs.h:128
GPP_E10
#define GPP_E10
Definition:
gpio_soc_defs.h:638
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPD8
#define GPD8
Definition:
gpio_soc_defs.h:389
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_B23
#define GPP_B23
Definition:
gpio_soc_defs.h:76
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_E16
#define GPP_E16
Definition:
gpio_soc_defs.h:644
GPP_D19
#define GPP_D19
Definition:
gpio_soc_defs.h:271
GPP_C1
#define GPP_C1
Definition:
gpio_soc_defs.h:538
GPP_F2
#define GPP_F2
Definition:
gpio_soc_defs.h:575
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPD6
#define GPD6
Definition:
gpio_soc_defs.h:387
GPP_F18
#define GPP_F18
Definition:
gpio_soc_defs.h:591
GPP_B3
#define GPP_B3
Definition:
gpio_soc_defs.h:56
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
GPD4
#define GPD4
Definition:
gpio_soc_defs.h:385
GPP_F3
#define GPP_F3
Definition:
gpio_soc_defs.h:576
GPP_C3
#define GPP_C3
Definition:
gpio_soc_defs.h:540
GPP_E12
#define GPP_E12
Definition:
gpio_soc_defs.h:640
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPD5
#define GPD5
Definition:
gpio_soc_defs.h:386
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_B7
#define GPP_B7
Definition:
gpio_soc_defs.h:60
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
GPP_D23
#define GPP_D23
Definition:
gpio_soc_defs.h:133
GPP_G1
#define GPP_G1
Definition:
gpio_soc_defs.h:89
GPP_G7
#define GPP_G7
Definition:
gpio_soc_defs.h:95
GPP_G4
#define GPP_G4
Definition:
gpio_soc_defs.h:92
GPP_G2
#define GPP_G2
Definition:
gpio_soc_defs.h:90
GPP_G6
#define GPP_G6
Definition:
gpio_soc_defs.h:94
GPP_G0
#define GPP_G0
Definition:
gpio_soc_defs.h:88
GPP_D20
#define GPP_D20
Definition:
gpio_soc_defs.h:130
GPP_G3
#define GPP_G3
Definition:
gpio_soc_defs.h:91
GPP_G5
#define GPP_G5
Definition:
gpio_soc_defs.h:93
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.h:45
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.h:224
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI_SMI
#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:412
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_APIC_HIGH
#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst)
Definition:
gpio_defs.h:405
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_SCI
#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:432
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
src
mainboard
google
glados
variants
glados
include
variant
gpio.h
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