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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/io.h>
#include <arch/mmio.h>
#include <assert.h>
#include <console/uart.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <southbridge/intel/lynxpoint/iobp.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <types.h>
Go to the source code of this file.
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static pci_devfn_t | get_uart_pci_device (void) |
void | uart_bootblock_init (void) |
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static |
Definition at line 14 of file uart_init.c.
References dead_code_t, and PCI_DEV.
Referenced by uart_bootblock_init().
Definition at line 24 of file uart_init.c.
References clrbits32, get_uart_pci_device(), pch_iobp_update(), PCI_BASE_ADDRESS_0, PCI_COMMAND, PCI_COMMAND_MEMORY, PCI_DEV_INVALID, pci_or_config16(), pci_s_write_config16(), pci_s_write_config32(), pci_write_config32(), setbits32, SIO_IOBP_GPIODF, SIO_REG_PPR_CLOCK, SIO_REG_PPR_CLOCK_EN, SIO_REG_PPR_CLOCK_M_DIV, SIO_REG_PPR_CLOCK_N_DIV, SIO_REG_PPR_CLOCK_UPDATE, SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_LTR_MODE_MASK, SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT, uart_console_get_pci_bdf(), uart_lpss_init(), UART_PCI_ENABLE, and write32().
Referenced by bootblock_early_southbridge_init(), and bootblock_soc_early_init().