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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <boot/coreboot_tables.h>
#include <bootmode.h>
#include "board.h"
#include <security/tpm/tis.h>
Go to the source code of this file.
Functions | |
void | setup_chromeos_gpios (void) |
void | fill_lb_gpios (struct lb_gpios *gpios) |
int | tis_plat_irq_status (void) |
int | get_ec_is_trusted (void) |
Definition at line 36 of file chromeos.c.
References ACTIVE_HIGH, ACTIVE_LOW, ARRAY_SIZE, GPIO_AMP_ENABLE, GPIO_AP_EC_INT, GPIO_BACKLIGHT_ENABLE, GPIO_EC_IN_RW, gpio_get(), GPIO_H1_AP_INT, GPIO_SD_CD_L, and lb_add_gpios().
int get_ec_is_trusted | ( | void | ) |
Definition at line 61 of file chromeos.c.
References GPIO_EC_IN_RW, and gpio_get().
Definition at line 8 of file chromeos.c.
References CONFIG, GPIO_AMP_ENABLE, GPIO_AP_EC_INT, GPIO_AVDD_LCD_ENABLE, GPIO_AVEE_LCD_ENABLE, GPIO_BACKLIGHT_ENABLE, GPIO_EC_IN_RW, GPIO_EDP_BRIDGE_ENABLE, GPIO_EN_FP_RAILS, GPIO_EN_PP3300_DX_EDP, GPIO_FP_RST_L, GPIO_FPMCU_BOOT0, GPIO_H1_AP_INT, gpio_input_irq(), gpio_input_pullup(), GPIO_MIPI_1V8_ENABLE, gpio_output(), GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE, GPIO_PS8640_EDP_BRIDGE_RST_L, GPIO_PULL_UP, GPIO_SD_CD_L, GPIO_VDD_RESET_1V8, and IRQ_TYPE_RISING_EDGE.
int tis_plat_irq_status | ( | void | ) |
Definition at line 56 of file chromeos.c.
References GPIO_H1_AP_INT.