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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <acpi/acpi.h>
#include <acpi/acpi_pm.h>
#include <device/device.h>
#include <device/pci.h>
#include <elog.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include <stdint.h>
Go to the source code of this file.
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static void | log_power_and_resets (const struct chipset_power_state *ps) |
static void | log_wake_events (const struct chipset_power_state *ps) |
void | southcluster_log_state (void) |
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Definition at line 12 of file elog.c.
References elog_add_event(), ELOG_TYPE_POWER_BUTTON_OVERRIDE, ELOG_TYPE_POWER_FAIL, ELOG_TYPE_PWROK_FAIL, ELOG_TYPE_RESET_BUTTON, ELOG_TYPE_RTC_RESET, ELOG_TYPE_SUS_POWER_FAIL, ELOG_TYPE_SYSTEM_RESET, ELOG_TYPE_TCO_RESET, chipset_power_state::gen_pmcon1, GEN_RST_STS, chipset_power_state::pm1_sts, PRBTNOR_STS, PWR_FLR, RPS, SECOND_TO_STS, SRS, SUS_PWR_FLR, and chipset_power_state::tco_sts.
Referenced by southcluster_log_state().
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Definition at line 38 of file elog.c.
References acpi_is_wakeup_s3(), ACPI_S3, ACPI_S5, elog_add_event_byte(), elog_add_event_wake(), ELOG_TYPE_ACPI_WAKE, ELOG_WAKE_SOURCE_GPE, ELOG_WAKE_SOURCE_PCIE, ELOG_WAKE_SOURCE_PME_INTERNAL, ELOG_WAKE_SOURCE_PWRBTN, ELOG_WAKE_SOURCE_RTC, chipset_power_state::gpe0_en, chipset_power_state::gpe0_sts, PCI_EXP_STS, PCIE_WAKE0_STS, PCIE_WAKE1_STS, PCIE_WAKE2_STS, PCIE_WAKE3_STS, chipset_power_state::pm1_sts, PME_B0_EN, PWRBTN_STS, RTC_STS, SUS_GPIO_STS0, and WAK_STS.
Referenced by southcluster_log_state().
Definition at line 76 of file elog.c.
References acpi_pm_state_for_elog(), log_power_and_resets(), and log_wake_events().
Referenced by smm_southbridge_clear_state().