coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
elog.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <acpi/acpi.h>
4 #include <acpi/acpi_pm.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <elog.h>
8 #include <soc/iomap.h>
9 #include <soc/pm.h>
10 #include <stdint.h>
11 
12 static void log_power_and_resets(const struct chipset_power_state *ps)
13 {
14  if (ps->gen_pmcon1 & PWR_FLR) {
17  }
18 
19  if (ps->gen_pmcon1 & SUS_PWR_FLR)
21 
22  if (ps->gen_pmcon1 & RPS)
24 
25  if (ps->tco_sts & SECOND_TO_STS)
27 
28  if (ps->pm1_sts & PRBTNOR_STS)
30 
31  if (ps->gen_pmcon1 & SRS)
33 
34  if (ps->gen_pmcon1 & GEN_RST_STS)
36 }
37 
38 static void log_wake_events(const struct chipset_power_state *ps)
39 {
40  const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS |
42 
43  uint32_t gpe0_sts;
44  uint32_t gpio_mask;
45  int i;
46 
47  /* Mask off disabled events. */
48  gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
49 
50  if (ps->pm1_sts & WAK_STS)
53 
54  if (ps->pm1_sts & PWRBTN_STS)
56 
57  if (ps->pm1_sts & RTC_STS)
59 
60  if (gpe0_sts & PME_B0_EN)
62 
63  if (gpe0_sts & pcie_wake_mask)
65 
66  gpio_mask = SUS_GPIO_STS0;
67  i = 0;
68  while (gpio_mask) {
69  if (gpio_mask & gpe0_sts)
71  gpio_mask <<= 1;
72  i++;
73  }
74 }
75 
77 {
78  const struct chipset_power_state *ps;
79 
80  if (acpi_pm_state_for_elog(&ps) < 0)
81  return;
82 
84  log_wake_events(ps);
85 }
int acpi_pm_state_for_elog(const struct chipset_power_state **ps)
Definition: acpi_pm.c:41
#define PME_B0_EN
Definition: pm.h:104
#define PCI_EXP_STS
Definition: pm.h:94
#define PRBTNOR_STS
Definition: pm.h:15
#define SRS
Definition: pm.h:160
static int acpi_is_wakeup_s3(void)
Definition: acpi.h:9
#define PCIE_WAKE2_STS
Definition: pm.h:164
#define SECOND_TO_STS
Definition: pm.h:227
#define SUS_GPIO_STS0
Definition: pm.h:159
#define PCIE_WAKE1_STS
Definition: pm.h:165
#define PCIE_WAKE3_STS
Definition: pm.h:163
#define GEN_RST_STS
Definition: pm.h:48
#define PCIE_WAKE0_STS
Definition: pm.h:168
#define PWRBTN_STS
Definition: southbridge.h:30
#define WAK_STS
Definition: southbridge.h:27
#define RTC_STS
Definition: southbridge.h:29
#define ELOG_WAKE_SOURCE_RTC
Definition: elog.h:154
#define ELOG_TYPE_RESET_BUTTON
Definition: elog.h:137
#define ELOG_WAKE_SOURCE_PCIE
Definition: elog.h:151
#define ELOG_TYPE_PWROK_FAIL
Definition: elog.h:130
#define ELOG_TYPE_SUS_POWER_FAIL
Definition: elog.h:129
#define ELOG_TYPE_POWER_FAIL
Definition: elog.h:128
#define ELOG_TYPE_ACPI_WAKE
Definition: elog.h:149
#define ELOG_WAKE_SOURCE_GPE
Definition: elog.h:155
#define ELOG_WAKE_SOURCE_PWRBTN
Definition: elog.h:157
#define ELOG_WAKE_SOURCE_PME_INTERNAL
Definition: elog.h:153
#define ELOG_TYPE_POWER_BUTTON_OVERRIDE
Definition: elog.h:134
#define ELOG_TYPE_SYSTEM_RESET
Definition: elog.h:138
#define ELOG_TYPE_RTC_RESET
Definition: elog.h:139
#define ELOG_TYPE_TCO_RESET
Definition: elog.h:140
int elog_add_event_byte(u8 event_type, u8 data)
Definition: elog.c:868
int elog_add_event_wake(u8 source, u32 instance)
Definition: elog.c:883
int elog_add_event(u8 event_type)
Definition: elog.c:863
#define RPS
Definition: i440bx.h:45
@ ACPI_S5
Definition: acpi.h:1385
@ ACPI_S3
Definition: acpi.h:1383
#define PWR_FLR
Definition: pmc.h:30
#define SUS_PWR_FLR
Definition: pmc.h:28
static void log_wake_events(const struct chipset_power_state *ps)
Definition: elog.c:38
void southcluster_log_state(void)
Definition: elog.c:76
static void log_power_and_resets(const struct chipset_power_state *ps)
Definition: elog.c:12
unsigned int uint32_t
Definition: stdint.h:14
uint32_t tco_sts
Definition: pm.h:249
uint32_t gpe0_en[4]
Definition: pm.h:148
uint32_t gpe0_sts[4]
Definition: pm.h:147
uint32_t gen_pmcon1
Definition: pm.h:231
uint16_t pm1_sts
Definition: pm.h:142