coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
bootblock_common.h
>
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#include <
device/pnp_ops.h
>
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#include <
northbridge/intel/sandybridge/raminit_native.h
>
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#include <
southbridge/intel/bd82x6x/pch.h
>
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#include <
superio/nuvoton/common/nuvoton.h
>
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#include <
superio/nuvoton/nct6779d/nct6779d.h
>
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#define GLOBAL_DEV PNP_DEV(0x2e, 0)
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#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
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const
struct
southbridge_usb_port
mainboard_usb_ports
[] = {
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{ 1, 0, 0 },
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{ 1, 0, 0 },
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{ 1, 0, 1 },
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{ 1, 0, 1 },
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{ 1, 0, 2 },
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{ 1, 0, 2 },
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{ 1, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 0, 4 },
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{ 1, 0, 4 },
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{ 1, 0, 6 },
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{ 1, 0, 5 },
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{ 1, 0, 5 },
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{ 1, 0, 6 },
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};
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void
bootblock_mainboard_early_init
(
void
)
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{
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nuvoton_pnp_enter_conf_state
(
GLOBAL_DEV
);
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/* Select SIO pin states */
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pnp_write_config
(
GLOBAL_DEV
, 0x1a, 0x00);
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pnp_write_config
(
GLOBAL_DEV
, 0x1c, 0x71);
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pnp_write_config
(
GLOBAL_DEV
, 0x1d, 0x0e);
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pnp_write_config
(
GLOBAL_DEV
, 0x22, 0xd7);
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pnp_write_config
(
GLOBAL_DEV
, 0x2a, 0x48);
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pnp_write_config
(
GLOBAL_DEV
, 0x2c, 0x00);
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/* Power RAM in S3 */
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pnp_set_logical_device
(
ACPI_DEV
);
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pnp_write_config
(
ACPI_DEV
, 0xe4, 0x10);
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nuvoton_pnp_exit_conf_state
(
GLOBAL_DEV
);
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/* Do not enable UART, the header is not populated by default */
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}
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void
mainboard_get_spd
(
spd_raw_data
*spd,
bool
id_only)
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{
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read_spd
(&spd[0], 0x50, id_only);
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read_spd
(&spd[2], 0x52, id_only);
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}
bootblock_common.h
spd_raw_data
u8 spd_raw_data[256]
Definition:
ddr3.h:156
bootblock_mainboard_early_init
void bootblock_mainboard_early_init(void)
Definition:
early_init.c:11
mainboard_get_spd
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition:
early_init.c:25
mainboard_usb_ports
const struct southbridge_usb_port mainboard_usb_ports[]
Definition:
early_init.c:8
ACPI_DEV
#define ACPI_DEV
Definition:
early_init.c:11
GLOBAL_DEV
#define GLOBAL_DEV
Definition:
early_init.c:10
nct6779d.h
read_spd
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition:
raminit.c:138
nuvoton_pnp_enter_conf_state
void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
Definition:
early_serial.c:33
nuvoton_pnp_exit_conf_state
void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
Definition:
early_serial.c:41
nuvoton.h
pnp_set_logical_device
void pnp_set_logical_device(struct device *dev)
Definition:
pnp_device.c:59
pnp_write_config
void pnp_write_config(struct device *dev, u8 reg, u8 value)
Definition:
pnp_device.c:38
pnp_ops.h
raminit_native.h
pch.h
southbridge_usb_port
Definition:
pch.h:56
src
mainboard
asus
h61-series
variants
p8h61-m_lx3_r2_0
early_init.c
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