coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
l2_cache.c File Reference
#include <stdint.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/l2_cache.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
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Data Structures

struct  latency_entry
 

Functions

int calculate_l2_latency (void)
 
int signal_l2 (u32 address, u32 data_high, u32 data_low, int way, u8 command)
 
int read_l2 (u32 address)
 
int write_l2 (u32 address, u32 data)
 
int test_l2_address_alias (u32 address1, u32 address2, u32 data_high, u32 data_low)
 
int calculate_l2_cache_size (void)
 
int calculate_l2_physical_address_range (void)
 
int set_l2_ecc (void)
 
int p6_configure_l2_cache (void)
 

Variables

static const struct latency_entry latency_650_t0 []
 
static const struct latency_entry latency_650_t1 []
 
static const struct latency_entry latency_670_t0 []
 
static const struct latency_entry latency_670_t1 []
 
static const struct latency_entry latency_670_t2 []
 
static const struct latency_entrylatency_650 []
 
static const struct latency_entrylatency_670 []
 

Function Documentation

◆ calculate_l2_cache_size()

int calculate_l2_cache_size ( void  )

Definition at line 332 of file l2_cache.c.

References address, BBL_CR_CTL3, BBLCR3_L2_SIZE, BBLCR3_L2_SIZE_256K, BBLCR3_L2_SIZE_4M, BIOS_DEBUG, c, msr_struct::lo, printk, rdmsr(), read_l2(), test_l2_address_alias(), write_l2(), and wrmsr().

Referenced by p6_configure_l2_cache().

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◆ calculate_l2_latency()

int calculate_l2_latency ( void  )

Definition at line 108 of file l2_cache.c.

References BBL_CR_CTL3, BIOS_DEBUG, cpuid_eax(), EBL_CR_POWERON, msr_struct::hi, IA32_PLATFORM_ID, latency_entry::key, latency_650, latency_670, msr_struct::lo, printk, rdmsr(), read_l2(), latency_entry::value, and wrmsr().

Referenced by p6_configure_l2_cache().

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◆ calculate_l2_physical_address_range()

int calculate_l2_physical_address_range ( void  )

Definition at line 487 of file l2_cache.c.

References BBL_CR_CTL3, BBLCR3_L2_PHYSICAL_RANGE, BIOS_DEBUG, msr_struct::lo, printk, rdmsr(), read_l2(), and wrmsr().

Referenced by p6_configure_l2_cache().

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◆ p6_configure_l2_cache()

◆ read_l2()

int read_l2 ( u32  address)

Definition at line 236 of file l2_cache.c.

References address, BBL_CR_ADDR, L2CMD_CR, msr_struct::lo, rdmsr(), and signal_l2().

Referenced by calculate_l2_cache_size(), calculate_l2_latency(), calculate_l2_physical_address_range(), p6_configure_l2_cache(), and write_l2().

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◆ set_l2_ecc()

int set_l2_ecc ( void  )

Definition at line 519 of file l2_cache.c.

References BBL_CR_CTL, BBL_CR_CTL3, BBL_CR_DECC, BBLCR3_L2_ECC_CHECK_ENABLE, BBLCR3_L2_SUPPLIED_ECC, BIOS_DEBUG, msr_struct::hi, msr_struct::lo, printk, rdmsr(), test_l2_address_alias(), and wrmsr().

Referenced by p6_configure_l2_cache().

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◆ signal_l2()

int signal_l2 ( u32  address,
u32  data_high,
u32  data_low,
int  way,
u8  command 
)

Definition at line 196 of file l2_cache.c.

References address, BBL_CR_ADDR, BBL_CR_BUSY, BBL_CR_CTL, BBL_CR_D0, BBL_CR_D3, BBL_CR_TRIG, msr_struct::hi, msr_struct::lo, rdmsr(), and wrmsr().

Referenced by p6_configure_l2_cache(), read_l2(), test_l2_address_alias(), and write_l2().

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◆ test_l2_address_alias()

int test_l2_address_alias ( u32  address1,
u32  address2,
u32  data_high,
u32  data_low 
)

Definition at line 301 of file l2_cache.c.

References BBL_CR_D0, BBL_CR_D3, msr_struct::hi, L2CMD_TRR, L2CMD_TWW, msr_struct::lo, rdmsr(), and signal_l2().

Referenced by calculate_l2_cache_size(), and set_l2_ecc().

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◆ write_l2()

int write_l2 ( u32  address,
u32  data 
)

Definition at line 251 of file l2_cache.c.

References address, read_l2(), and signal_l2().

Referenced by calculate_l2_cache_size(), and p6_configure_l2_cache().

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Variable Documentation

◆ latency_650

const struct latency_entry* latency_650[]
static
Initial value:
= {
}
static const struct latency_entry latency_650_t1[]
Definition: l2_cache.c:75
static const struct latency_entry latency_650_t0[]
Definition: l2_cache.c:69

Definition at line 99 of file l2_cache.c.

Referenced by calculate_l2_latency().

◆ latency_650_t0

const struct latency_entry latency_650_t0[]
static
Initial value:
= {
{0x10, 0x02}, {0x50, 0x02}, {0x20, 0x04}, {0x60, 0x06},
{0x00, 0x08}, {0x40, 0x0C}, {0x12, 0x06}, {0x52, 0x0A},
{0x22, 0x0E}, {0x62, 0x10}, {0x02, 0x10}, {0xFF, 0x00}
}

Definition at line 1 of file l2_cache.c.

◆ latency_650_t1

const struct latency_entry latency_650_t1[]
static
Initial value:
= {
{0x12, 0x14}, {0x52, 0x16}, {0x22, 0x16}, {0x62, 0x16},
{0xFF, 0x00}
}

Definition at line 1 of file l2_cache.c.

◆ latency_670

const struct latency_entry* latency_670[]
static
Initial value:
= {
}
static const struct latency_entry latency_670_t2[]
Definition: l2_cache.c:92
static const struct latency_entry latency_670_t1[]
Definition: l2_cache.c:87
static const struct latency_entry latency_670_t0[]
Definition: l2_cache.c:80

Definition at line 104 of file l2_cache.c.

Referenced by calculate_l2_latency().

◆ latency_670_t0

const struct latency_entry latency_670_t0[]
static
Initial value:
= {
{0x60, 0x06}, {0x00, 0x08}, {0x12, 0x06}, {0x52, 0x0A},
{0x22, 0x0E}, {0x62, 0x10}, {0x02, 0x10}, {0x42, 0x02},
{0x11, 0x0E}, {0x51, 0x0C}, {0x21, 0x02}, {0x61, 0x10},
{0x01, 0x10}, {0x41, 0x02}, {0xFF, 0x00}
}

Definition at line 1 of file l2_cache.c.

◆ latency_670_t1

const struct latency_entry latency_670_t1[]
static
Initial value:
= {
{0x22, 0x18}, {0x62, 0x18}, {0x02, 0x1A}, {0x11, 0x18},
{0xFF, 0x00}
}

Definition at line 1 of file l2_cache.c.

◆ latency_670_t2

const struct latency_entry latency_670_t2[]
static
Initial value:
= {
{0x22, 0x12}, {0x62, 0x14}, {0x02, 0x16}, {0x42, 0x1E},
{0x11, 0x12}, {0x51, 0x16}, {0x21, 0x1E}, {0x61, 0x14},
{0x01, 0x16}, {0x41, 0x1E}, {0xFF, 0x00}
}

Definition at line 1 of file l2_cache.c.