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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <cbmem.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <boot/tables.h>
#include <acpi/acpi.h>
#include <northbridge/intel/x4x/memmap.h>
#include <northbridge/intel/x4x/chip.h>
#include <northbridge/intel/x4x/x4x.h>
#include <cpu/intel/smm_reloc.h>
Go to the source code of this file.
Functions | |
static void | mch_domain_read_resources (struct device *dev) |
static void | mch_domain_set_resources (struct device *dev) |
static void | mch_domain_init (struct device *dev) |
static const char * | northbridge_acpi_name (const struct device *dev) |
void | northbridge_write_smram (u8 smram) |
static void | enable_dev (struct device *dev) |
static void | hide_pci_fn (const int dev_bit_base, const struct device *dev) |
static void | hide_pci_dev (const int dev, int functions, const int dev_bit_base) |
static void | x4x_init (void *const chip_info) |
Variables | |
static const int | legacy_hole_base_k = 0xa0000 / 1024 |
static struct device_operations | pci_domain_ops |
static struct device_operations | cpu_bus_ops |
struct chip_operations | northbridge_intel_x4x_ops |
Definition at line 172 of file northbridge.c.
References cpu_bus_ops, DEVICE_PATH_CPU_CLUSTER, DEVICE_PATH_DOMAIN, device::ops, device::path, pci_domain_ops, and device_path::type.
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Definition at line 190 of file northbridge.c.
References hide_pci_fn(), and pcidev_on_root().
Definition at line 181 of file northbridge.c.
References D0F0_DEVEN, pci_path::devfn, device::enabled, device::path, device_path::pci, PCI_FUNC, pci_update_config32(), and pcidev_on_root().
Referenced by hide_pci_dev().
Definition at line 124 of file northbridge.c.
References PCI_COMMAND, PCI_COMMAND_SERR, and pci_or_config16().
Definition at line 18 of file northbridge.c.
References BIOS_DEBUG, BIOS_INFO, cbmem_top(), D0F0_ESMRAMC, D0F0_GGC, D0F0_TOLUD, D0F0_TOM, D0F0_TOUUD, decode_igd_gtt_size(), decode_igd_memory_size(), decode_tseg_size(), DEFAULT_HECIBAR, fixed_mem_resource(), GiB, IORESOURCE_RESERVE, KiB, legacy_hole_base_k, mmconf_resource(), mmio_resource, pci_domain_read_resources(), pci_read_config16(), pci_read_config8(), pcidev_on_root(), printk, ram_resource, reserved_ram_resource, and uma_resource.
Definition at line 114 of file northbridge.c.
References assign_resources(), device::link_list, resource::next, report_resource_stored(), and device::resource_list.
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Definition at line 130 of file northbridge.c.
References device::bus, pci_path::devfn, DEVICE_PATH_DOMAIN, DEVICE_PATH_PCI, NULL, device::path, device_path::pci, PCI_DEVFN, bus::secondary, and device_path::type.
Definition at line 146 of file northbridge.c.
References PCI_DEV, pci_write_config8(), and SMRAMC.
Referenced by smm_lock().
Definition at line 196 of file northbridge.c.
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Definition at line 146 of file northbridge.c.
Referenced by enable_dev().
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Definition at line 16 of file northbridge.c.
Referenced by mch_domain_read_resources().
struct chip_operations northbridge_intel_x4x_ops |
Definition at line 196 of file northbridge.c.
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Definition at line 146 of file northbridge.c.
Referenced by enable_dev().