coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#ifndef MAINBOARD_GPIO_H
4
#define MAINBOARD_GPIO_H
5
6
#include <soc/gpe.h>
7
#include <soc/gpio.h>
8
9
/* EC in RW */
10
#define GPIO_EC_IN_RW GPP_C6
11
12
/* BIOS Flash Write Protect */
13
#define GPIO_PCH_WP GPP_C23
14
15
/* Memory configuration board straps */
16
#define GPIO_MEM_CONFIG_0 GPP_C12
17
#define GPIO_MEM_CONFIG_1 GPP_C13
18
#define GPIO_MEM_CONFIG_2 GPP_C14
19
#define GPIO_MEM_CONFIG_3 GPP_C15
20
21
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
22
#define GPE_EC_WAKE GPE0_LAN_WAK
23
24
/* eSPI virtual wire reporting */
25
#define EC_SCI_GPI GPE0_ESPI
26
27
/* Power rail control signals */
28
#define EN_PP3300_DX_CAM GPP_D12
29
30
#ifndef __ACPI__
31
/* Pad configuration in ramstage */
32
/* Leave eSPI pins untouched from default settings */
33
static
const
struct
pad_config
gpio_table
[] = {
34
/* RCIN# */
PAD_NC
(
GPP_A0
,
NONE
),
/* TP41 */
35
/* ESPI_IO0 */
36
/* ESPI_IO1 */
37
/* ESPI_IO2 */
38
/* ESPI_IO3 */
39
/* ESPI_CS# */
40
/* SERIRQ */
PAD_NC
(
GPP_A6
,
NONE
),
/* TP44 */
41
/* PIRQA# */
PAD_NC
(
GPP_A7
,
NONE
),
42
/* CLKRUN# */
PAD_NC
(
GPP_A8
,
NONE
),
/* TP45 */
43
/* ESPI_CLK */
44
/* CLKOUT_LPC1 */
PAD_NC
(
GPP_A10
,
NONE
),
45
/* PME# */
PAD_NC
(
GPP_A11
,
NONE
),
/* TP67 */
46
/* BM_BUSY# */
PAD_NC
(
GPP_A12
,
NONE
),
47
/* SUSWARN# */
PAD_CFG_NF
(
GPP_A13
,
NONE
, DEEP, NF1),
48
/* ESPI_RESET# */
49
/* SUSACK# */
PAD_CFG_NF
(
GPP_A15
,
NONE
, DEEP, NF1),
50
/* SD_1P8_SEL */
PAD_NC
(
GPP_A16
,
NONE
),
51
/* SD_PWR_EN# */
PAD_NC
(
GPP_A17
,
NONE
),
52
/* ISH_GP0 */
PAD_NC
(
GPP_A18
,
NONE
),
53
/* ISH_GP1 */
PAD_NC
(
GPP_A19
,
NONE
),
54
/* ISH_GP2 */
PAD_NC
(
GPP_A20
,
NONE
),
55
/* ISH_GP3 */
PAD_NC
(
GPP_A21
,
NONE
),
56
/* ISH_GP4 */
PAD_NC
(
GPP_A22
,
NONE
),
57
/* ISH_GP5 */
PAD_NC
(
GPP_A23
,
NONE
),
58
59
/* CORE_VID0 */
PAD_NC
(
GPP_B0
,
NONE
),
/* TP42 */
60
/* CORE_VID1 */
PAD_NC
(
GPP_B1
,
NONE
),
/* TP43 */
61
/* VRALERT# */
PAD_NC
(
GPP_B2
,
NONE
),
62
/* CPU_GP2 */
PAD_CFG_GPI_APIC_HIGH
(
GPP_B3
,
NONE
, PLTRST),
/* TOUCHPAD_INT_L */
63
/* CPU_GP3 */
PAD_NC
(
GPP_B4
,
NONE
),
64
/* SRCCLKREQ0# */
PAD_NC
(
GPP_B5
,
NONE
),
65
/* SRCCLKREQ1# */
PAD_CFG_NF
(
GPP_B6
,
NONE
, DEEP, NF1),
/* WLAN CKLREQ */
66
/* SRCCLKREQ2# */
PAD_NC
(
GPP_B7
,
NONE
),
67
/* SRCCLKREQ3# */
PAD_NC
(
GPP_B8
,
NONE
),
68
/* SRCCLKREQ4# */
PAD_NC
(
GPP_B9
,
NONE
),
69
/* SRCCLKREQ5# */
PAD_NC
(
GPP_B10
,
NONE
),
70
/* EXT_PWR_GATE# */
PAD_NC
(
GPP_B11
,
NONE
),
71
/* SLP_S0# */
PAD_CFG_NF
(
GPP_B12
,
NONE
, DEEP, NF1),
72
/* PLTRST# */
PAD_CFG_NF
(
GPP_B13
,
NONE
, DEEP, NF1),
73
/* SPKR */
PAD_NC
(
GPP_B14
,
NONE
),
74
/* GSPI0_CS# */
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
/* DSP */
75
/* GSPI0_CLK */
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
/* DSP */
76
/* GSPI0_MISO */
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
/* DSP */
77
/* GSPI0_MOSI */
PAD_CFG_NF
(
GPP_B18
,
NONE
, DEEP, NF1),
/* DSP */
78
/* GSPI1_CS# */
PAD_NC
(
GPP_B19
,
NONE
),
79
/* GSPI1_CLK */
PAD_NC
(
GPP_B20
,
NONE
),
80
/* GSPI1_MISO */
PAD_NC
(
GPP_B21
,
NONE
),
81
/* GSPI1_MOSI */
PAD_NC
(
GPP_B22
,
NONE
),
82
/* SM1ALERT# */
PAD_NC
(
GPP_B23
,
NONE
),
83
84
/* SMBCLK */
PAD_NC
(
GPP_C0
,
NONE
),
85
/* SMBDATA */
PAD_NC
(
GPP_C1
,
NONE
),
86
/* SMBALERT# */
PAD_NC
(
GPP_C2
,
NONE
),
87
/* SML0CLK */
PAD_NC
(
GPP_C3
,
NONE
),
88
/* SML0DATA */
PAD_NC
(
GPP_C4
,
NONE
),
89
/* SML0ALERT# */
PAD_NC
(
GPP_C5
,
NONE
),
90
/* SM1CLK */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C6
, UP_20K,
91
DEEP),
/* EC_IN_RW */
92
/* SM1DATA */
PAD_NC
(
GPP_C7
,
NONE
),
93
/* UART0_RXD */
PAD_NC
(
GPP_C8
,
NONE
),
94
/* UART0_TXD */
PAD_NC
(
GPP_C9
,
NONE
),
95
/* UART0_RTS# */
PAD_NC
(
GPP_C10
,
NONE
),
96
/* UART0_CTS# */
PAD_NC
(
GPP_C11
,
NONE
),
97
/* UART1_RXD */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C12
,
NONE
,
98
DEEP),
/* MEM_CONFIG[0] */
99
/* UART1_TXD */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C13
,
NONE
,
100
DEEP),
/* MEM_CONFIG[1] */
101
/* UART1_RTS# */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C14
,
NONE
,
102
DEEP),
/* MEM_CONFIG[2] */
103
/* UART1_CTS# */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C15
,
NONE
,
104
DEEP),
/* MEM_CONFIG[3] */
105
/* I2C0_SDA */
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
/* TOUCHSCREEN */
106
/* I2C0_SCL */
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
/* TOUCHSCREEN */
107
/* I2C1_SDA */
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
/* TPM */
108
/* I2C1_SCL */
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
/* TPM */
109
/* UART2_RXD */
PAD_CFG_NF
(
GPP_C20
,
NONE
, DEEP, NF1),
/* SERVO */
110
/* UART2_TXD */
PAD_CFG_NF
(
GPP_C21
,
NONE
, DEEP, NF1),
/* SERVO */
111
/* UART2_RTS# */
PAD_CFG_GPO
(
GPP_C22
, 1, DEEP),
/* EN_PP3300_DX_TOUCHSCREEN */
112
/* UART2_CTS# */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C23
, UP_20K,
113
DEEP),
/* PCH_WP */
114
115
/* SPI1_CS# */
PAD_CFG_GPO
(
GPP_D0
, 0, DEEP),
/* TOUCHPAD_BOOT */
116
/* SPI1_CLK */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_D1
,
NONE
,
117
DEEP),
/* TOUCHPAD_RESET */
118
/* SPI1_MISO */
PAD_NC
(
GPP_D2
,
NONE
),
119
/* SPI1_MOSI */
PAD_NC
(
GPP_D3
,
NONE
),
120
/* FASHTRIG */
PAD_NC
(
GPP_D4
,
NONE
),
121
/* ISH_I2C0_SDA */
PAD_NC
(
GPP_D5
,
NONE
),
122
/* ISH_I2C0_SCL */
PAD_NC
(
GPP_D6
,
NONE
),
123
/* ISH_I2C1_SDA */
PAD_NC
(
GPP_D7
,
NONE
),
124
/* ISH_I2C1_SCL */
PAD_NC
(
GPP_D8
,
NONE
),
125
/* ISH_SPI_CS# */
PAD_CFG_GPI_INT
(
GPP_D9
,
NONE
, PLTRST, EDGE_SINGLE),
/* HP_IRQ_GPIO */
126
/* ISH_SPI_CLK */
PAD_CFG_GPO
(
GPP_D10
, 1, DEEP),
/* SPKR_RST_L */
127
/* ISH_SPI_MISO */
PAD_CFG_GPI_APIC_HIGH
(
GPP_D11
,
NONE
, PLTRST),
/* SPKR_INT_L */
128
/* ISH_SPI_MOSI */
PAD_CFG_TERM_GPO
(
GPP_D12
, 1, UP_20K, DEEP),
/* EN_PP3300_DX_CAM */
129
/* ISH_UART0_RXD */
PAD_NC
(
GPP_D13
,
NONE
),
130
/* ISH_UART0_TXD */
PAD_NC
(
GPP_D14
,
NONE
),
131
/* ISH_UART0_RTS# */
PAD_NC
(
GPP_D15
,
NONE
),
132
/* ISH_UART0_CTS# */
PAD_NC
(
GPP_D16
,
NONE
),
133
/* DMIC_CLK1 */
PAD_NC
(
GPP_D17
,
NONE
),
134
/* DMIC_DATA1 */
PAD_NC
(
GPP_D18
,
NONE
),
135
/* DMIC_CLK0 */
PAD_CFG_NF
(
GPP_D19
,
NONE
, DEEP, NF1),
136
/* DMIC_DATA0 */
PAD_CFG_NF
(
GPP_D20
,
NONE
, DEEP, NF1),
137
/* SPI1_IO2 */
PAD_NC
(
GPP_D21
,
NONE
),
138
/* SPI1_IO3 */
PAD_CFG_GPO
(
GPP_D22
, 1, DEEP),
/* I2S2 BUFFER */
139
/* I2S_MCLK */
PAD_CFG_NF
(
GPP_D23
,
NONE
, DEEP, NF1),
140
141
/* SATAXPCI0 */
PAD_CFG_GPI_APIC_LOW
(
GPP_E0
,
NONE
, PLTRST),
/* TPM_INT_L */
142
/* SATAXPCIE1 */
PAD_NC
(
GPP_E1
,
NONE
),
143
/* SATAXPCIE2 */
PAD_NC
(
GPP_E2
,
NONE
),
144
/* CPU_GP0 */
PAD_NC
(
GPP_E3
,
NONE
),
145
/* SATA_DEVSLP0 */
PAD_NC
(
GPP_E4
,
NONE
),
146
/* SATA_DEVSLP1 */
PAD_NC
(
GPP_E5
,
NONE
),
147
/* SATA_DEVSLP2 */
PAD_NC
(
GPP_E6
,
NONE
),
148
/* CPU_GP1 */
PAD_CFG_GPI_APIC_HIGH
(
GPP_E7
,
NONE
, PLTRST),
/* TOUCHSCREEN_INT_L */
149
/* SATALED# */
PAD_NC
(
GPP_E8
,
NONE
),
150
/* USB2_OCO# */
PAD_CFG_NF
(
GPP_E9
,
NONE
, DEEP, NF1),
/* USB_C0_OC_ODL */
151
/* USB2_OC1# */
PAD_CFG_NF
(
GPP_E10
,
NONE
, DEEP, NF1),
/* USB_C1_OC_ODL */
152
/* USB2_OC2# */
PAD_CFG_GPO
(
GPP_E11
, 1, DEEP),
/* TOUCHSCREEN_STOP_L */
153
/* USB2_OC3# */
PAD_NC
(
GPP_E12
,
NONE
),
154
/* DDPB_HPD0 */
PAD_CFG_NF
(
GPP_E13
, DN_20K, DEEP, NF1),
/* USB_C0_DP_HPD */
155
/* DDPC_HPD1 */
PAD_CFG_NF
(
GPP_E14
, DN_20K, DEEP, NF1),
/* USB_C1_DP_HPD */
156
/* DDPD_HPD2 */
PAD_NC
(
GPP_E15
,
NONE
),
/* TP48 */
157
/* DDPE_HPD3 */
PAD_NC
(
GPP_E16
,
NONE
),
/* TP244 */
158
/* EDP_HPD */
PAD_CFG_NF
(
GPP_E17
,
NONE
, DEEP, NF1),
159
/* DDPB_CTRLCLK */
PAD_NC
(
GPP_E18
,
NONE
),
160
/* DDPB_CTRLDATA */
PAD_NC
(
GPP_E19
,
NONE
),
161
/* DDPC_CTRLCLK */
PAD_NC
(
GPP_E20
,
NONE
),
162
/* DDPC_CTRLDATA */
PAD_NC
(
GPP_E21
,
NONE
),
163
/* DDPD_CTRLCLK */
PAD_NC
(
GPP_E22
,
NONE
),
164
/* DDPD_CTRLDATA */
PAD_NC
(
GPP_E23
,
NONE
),
165
166
/* The next 4 pads are for bit banging the amplifiers, default to I2S */
167
/* I2S2_SCLK */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F0
,
NONE
, DEEP),
168
/* I2S2_SFRM */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F1
,
NONE
, DEEP),
169
/* I2S2_TXD */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F2
,
NONE
, DEEP),
170
/* I2S2_RXD */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F3
,
NONE
, DEEP),
171
/* I2C2_SDA */
PAD_CFG_NF_1V8(
GPP_F4
,
NONE
, DEEP, NF1),
/* TOUCHPAD */
172
/* I2C2_SCL */
PAD_CFG_NF_1V8(
GPP_F5
,
NONE
, DEEP, NF1),
/* TOUCHPAD */
173
/* I2C3_SDA */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F6
,
NONE
,
174
DEEP),
/* DISPLAY is master */
175
/* I2C3_SCL */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F7
,
NONE
,
176
DEEP),
/* DISPLAY is master */
177
/* I2C4_SDA */
PAD_CFG_NF_1V8(
GPP_F8
,
NONE
, DEEP, NF1),
/* AUDIO1V8_SDA */
178
/* I2C4_SCL */
PAD_CFG_NF_1V8(
GPP_F9
,
NONE
, DEEP, NF1),
/* AUDIO1V8_SCL */
179
/* I2C5_SDA */
PAD_CFG_GPI_APIC_HIGH
(
GPP_F10
,
NONE
, PLTRST),
/* MIC_INT_L */
180
/* I2C5_SCL */
PAD_NC
(
GPP_F11
,
NONE
),
/* TP109 */
181
/* EMMC_CMD */
PAD_CFG_NF
(
GPP_F12
,
NONE
, DEEP, NF1),
182
/* EMMC_DATA0 */
PAD_CFG_NF
(
GPP_F13
,
NONE
, DEEP, NF1),
183
/* EMMC_DATA1 */
PAD_CFG_NF
(
GPP_F14
,
NONE
, DEEP, NF1),
184
/* EMMC_DATA2 */
PAD_CFG_NF
(
GPP_F15
,
NONE
, DEEP, NF1),
185
/* EMMC_DATA3 */
PAD_CFG_NF
(
GPP_F16
,
NONE
, DEEP, NF1),
186
/* EMMC_DATA4 */
PAD_CFG_NF
(
GPP_F17
,
NONE
, DEEP, NF1),
187
/* EMMC_DATA5 */
PAD_CFG_NF
(
GPP_F18
,
NONE
, DEEP, NF1),
188
/* EMMC_DATA6 */
PAD_CFG_NF
(
GPP_F19
,
NONE
, DEEP, NF1),
189
/* EMMC_DATA7 */
PAD_CFG_NF
(
GPP_F20
,
NONE
, DEEP, NF1),
190
/* EMMC_RCLK */
PAD_CFG_NF
(
GPP_F21
,
NONE
, DEEP, NF1),
191
/* EMMC_CLK */
PAD_CFG_NF
(
GPP_F22
,
NONE
, DEEP, NF1),
192
/* RSVD */
PAD_NC
(
GPP_F23
,
NONE
),
193
194
/* SD_CMD */
PAD_NC
(
GPP_G0
,
NONE
),
195
/* SD_DATA0 */
PAD_NC
(
GPP_G1
,
NONE
),
196
/* SD_DATA1 */
PAD_NC
(
GPP_G2
,
NONE
),
197
/* SD_DATA2 */
PAD_NC
(
GPP_G3
,
NONE
),
198
/* SD_DATA3 */
PAD_NC
(
GPP_G4
,
NONE
),
199
/* SD_CD# */
PAD_NC
(
GPP_G5
,
NONE
),
200
/* SD_CLK */
PAD_NC
(
GPP_G6
,
NONE
),
201
/* SD_WP */
PAD_NC
(
GPP_G7
,
NONE
),
202
203
/* BATLOW# */
PAD_CFG_NF
(
GPD0
,
NONE
, DEEP, NF1),
204
/* ACPRESENT */
PAD_CFG_NF
(
GPD1
, UP_20K, DEEP, NF1),
205
/* LAN_WAKE# */
PAD_CFG_NF
(
GPD2
,
NONE
, DEEP, NF1),
/* EC_PCH_WAKE_L */
206
/* PWRBTN# */
PAD_CFG_NF
(
GPD3
, UP_20K, DEEP, NF1),
207
/* SLP_S3# */
PAD_CFG_NF
(
GPD4
,
NONE
, DEEP, NF1),
208
/* SLP_S4# */
PAD_CFG_NF
(
GPD5
,
NONE
, DEEP, NF1),
209
/* SLP_A# */
PAD_NC
(
GPD6
,
NONE
),
/* TP26 */
210
/* RSVD */
PAD_NC
(
GPD7
,
NONE
),
211
/* SUSCLK */
PAD_CFG_NF
(
GPD8
,
NONE
, DEEP, NF1),
212
/* SLP_WLAN# */
PAD_NC
(
GPD9
,
NONE
),
/* TP25 */
213
/* SLP_S5# */
PAD_NC
(
GPD10
,
NONE
),
/* TP15 */
214
/* LANPHYC */
PAD_NC
(
GPD11
,
NONE
),
215
};
216
217
/* Early pad configuration in bootblock */
218
static
const
struct
pad_config
early_gpio_table
[] = {
219
/* I2C1_SDA */
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
/* TPM */
220
/* I2C1_SCL */
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
/* TPM */
221
/* UART2_CTS# */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C23
, UP_20K,
222
DEEP),
/* PCH_WP */
223
/* SATAXPCI0 */
PAD_CFG_GPI_APIC_LOW
(
GPP_E0
,
NONE
, PLTRST),
/* TPM_INT_L */
224
225
/* Ensure UART pins are in native mode for H1 */
226
/* UART2_RXD */
PAD_CFG_NF
(
GPP_C20
,
NONE
, DEEP, NF1),
/* SERVO */
227
/* UART2_TXD */
PAD_CFG_NF
(
GPP_C21
,
NONE
, DEEP, NF1),
/* SERVO */
228
229
/* SM1CLK */
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C6
, UP_20K,
230
DEEP),
/* EC_IN_RW */
231
};
232
233
#endif
234
235
#endif
GPD11
#define GPD11
Definition:
gpio_soc_defs.h:392
GPP_C15
#define GPP_C15
Definition:
gpio_soc_defs.h:552
GPD3
#define GPD3
Definition:
gpio_soc_defs.h:384
GPP_B6
#define GPP_B6
Definition:
gpio_soc_defs.h:59
GPP_D1
#define GPP_D1
Definition:
gpio_soc_defs.h:253
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_C2
#define GPP_C2
Definition:
gpio_soc_defs.h:539
GPP_D10
#define GPP_D10
Definition:
gpio_soc_defs.h:262
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_E3
#define GPP_E3
Definition:
gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F21
#define GPP_F21
Definition:
gpio_soc_defs.h:594
GPP_C12
#define GPP_C12
Definition:
gpio_soc_defs.h:549
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_F16
#define GPP_F16
Definition:
gpio_soc_defs.h:589
GPP_E0
#define GPP_E0
Definition:
gpio_soc_defs.h:628
GPP_F6
#define GPP_F6
Definition:
gpio_soc_defs.h:579
GPP_D14
#define GPP_D14
Definition:
gpio_soc_defs.h:266
GPP_B1
#define GPP_B1
Definition:
gpio_soc_defs.h:54
GPP_F20
#define GPP_F20
Definition:
gpio_soc_defs.h:593
GPP_F23
#define GPP_F23
Definition:
gpio_soc_defs.h:596
GPP_C5
#define GPP_C5
Definition:
gpio_soc_defs.h:542
GPP_B12
#define GPP_B12
Definition:
gpio_soc_defs.h:65
GPP_D12
#define GPP_D12
Definition:
gpio_soc_defs.h:264
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_B2
#define GPP_B2
Definition:
gpio_soc_defs.h:55
GPP_D7
#define GPP_D7
Definition:
gpio_soc_defs.h:259
GPP_B13
#define GPP_B13
Definition:
gpio_soc_defs.h:66
GPP_E6
#define GPP_E6
Definition:
gpio_soc_defs.h:634
GPP_F0
#define GPP_F0
Definition:
gpio_soc_defs.h:573
GPP_D6
#define GPP_D6
Definition:
gpio_soc_defs.h:258
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_D2
#define GPP_D2
Definition:
gpio_soc_defs.h:254
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPD0
#define GPD0
Definition:
gpio_soc_defs.h:380
GPP_D9
#define GPP_D9
Definition:
gpio_soc_defs.h:261
GPP_F5
#define GPP_F5
Definition:
gpio_soc_defs.h:578
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_E13
#define GPP_E13
Definition:
gpio_soc_defs.h:641
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_D11
#define GPP_D11
Definition:
gpio_soc_defs.h:263
GPP_A6
#define GPP_A6
Definition:
gpio_soc_defs.h:125
GPP_C11
#define GPP_C11
Definition:
gpio_soc_defs.h:548
GPP_D5
#define GPP_D5
Definition:
gpio_soc_defs.h:257
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_F9
#define GPP_F9
Definition:
gpio_soc_defs.h:582
GPP_C13
#define GPP_C13
Definition:
gpio_soc_defs.h:550
GPP_E14
#define GPP_E14
Definition:
gpio_soc_defs.h:642
GPP_E23
#define GPP_E23
Definition:
gpio_soc_defs.h:651
GPP_E9
#define GPP_E9
Definition:
gpio_soc_defs.h:637
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_E8
#define GPP_E8
Definition:
gpio_soc_defs.h:636
GPP_A7
#define GPP_A7
Definition:
gpio_soc_defs.h:126
GPP_E5
#define GPP_E5
Definition:
gpio_soc_defs.h:633
GPP_A0
#define GPP_A0
Definition:
gpio_soc_defs.h:119
GPD7
#define GPD7
Definition:
gpio_soc_defs.h:388
GPP_B8
#define GPP_B8
Definition:
gpio_soc_defs.h:61
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_B20
#define GPP_B20
Definition:
gpio_soc_defs.h:73
GPP_A20
#define GPP_A20
Definition:
gpio_soc_defs.h:139
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_F1
#define GPP_F1
Definition:
gpio_soc_defs.h:574
GPP_F17
#define GPP_F17
Definition:
gpio_soc_defs.h:590
GPP_A12
#define GPP_A12
Definition:
gpio_soc_defs.h:131
GPP_F15
#define GPP_F15
Definition:
gpio_soc_defs.h:588
GPP_D4
#define GPP_D4
Definition:
gpio_soc_defs.h:256
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_C6
#define GPP_C6
Definition:
gpio_soc_defs.h:543
GPD2
#define GPD2
Definition:
gpio_soc_defs.h:383
GPP_F10
#define GPP_F10
Definition:
gpio_soc_defs.h:583
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_F7
#define GPP_F7
Definition:
gpio_soc_defs.h:580
GPD1
#define GPD1
Definition:
gpio_soc_defs.h:382
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_D18
#define GPP_D18
Definition:
gpio_soc_defs.h:270
GPP_B19
#define GPP_B19
Definition:
gpio_soc_defs.h:72
GPP_E17
#define GPP_E17
Definition:
gpio_soc_defs.h:645
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_E19
#define GPP_E19
Definition:
gpio_soc_defs.h:647
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPD10
#define GPD10
Definition:
gpio_soc_defs.h:391
GPP_E18
#define GPP_E18
Definition:
gpio_soc_defs.h:646
GPP_F14
#define GPP_F14
Definition:
gpio_soc_defs.h:587
GPP_F4
#define GPP_F4
Definition:
gpio_soc_defs.h:577
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_D0
#define GPP_D0
Definition:
gpio_soc_defs.h:252
GPP_B14
#define GPP_B14
Definition:
gpio_soc_defs.h:67
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_D13
#define GPP_D13
Definition:
gpio_soc_defs.h:265
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_B5
#define GPP_B5
Definition:
gpio_soc_defs.h:58
GPP_B0
#define GPP_B0
Definition:
gpio_soc_defs.h:53
GPP_A11
#define GPP_A11
Definition:
gpio_soc_defs.h:130
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_E20
#define GPP_E20
Definition:
gpio_soc_defs.h:648
GPP_A15
#define GPP_A15
Definition:
gpio_soc_defs.h:134
GPP_E10
#define GPP_E10
Definition:
gpio_soc_defs.h:638
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPD8
#define GPD8
Definition:
gpio_soc_defs.h:389
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_A21
#define GPP_A21
Definition:
gpio_soc_defs.h:140
GPP_B23
#define GPP_B23
Definition:
gpio_soc_defs.h:76
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_E16
#define GPP_E16
Definition:
gpio_soc_defs.h:644
GPP_D19
#define GPP_D19
Definition:
gpio_soc_defs.h:271
GPP_C1
#define GPP_C1
Definition:
gpio_soc_defs.h:538
GPP_F2
#define GPP_F2
Definition:
gpio_soc_defs.h:575
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPD6
#define GPD6
Definition:
gpio_soc_defs.h:387
GPP_F18
#define GPP_F18
Definition:
gpio_soc_defs.h:591
GPP_B3
#define GPP_B3
Definition:
gpio_soc_defs.h:56
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
GPP_D15
#define GPP_D15
Definition:
gpio_soc_defs.h:267
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPP_B21
#define GPP_B21
Definition:
gpio_soc_defs.h:74
GPD4
#define GPD4
Definition:
gpio_soc_defs.h:385
GPP_B4
#define GPP_B4
Definition:
gpio_soc_defs.h:57
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_F3
#define GPP_F3
Definition:
gpio_soc_defs.h:576
GPP_E22
#define GPP_E22
Definition:
gpio_soc_defs.h:650
GPP_E21
#define GPP_E21
Definition:
gpio_soc_defs.h:649
GPP_C3
#define GPP_C3
Definition:
gpio_soc_defs.h:540
GPP_E12
#define GPP_E12
Definition:
gpio_soc_defs.h:640
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_E4
#define GPP_E4
Definition:
gpio_soc_defs.h:632
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPD5
#define GPD5
Definition:
gpio_soc_defs.h:386
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_B7
#define GPP_B7
Definition:
gpio_soc_defs.h:60
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
GPP_D3
#define GPP_D3
Definition:
gpio_soc_defs.h:255
GPP_D23
#define GPP_D23
Definition:
gpio_soc_defs.h:133
GPP_G1
#define GPP_G1
Definition:
gpio_soc_defs.h:89
GPP_G7
#define GPP_G7
Definition:
gpio_soc_defs.h:95
GPP_D22
#define GPP_D22
Definition:
gpio_soc_defs.h:132
GPP_G4
#define GPP_G4
Definition:
gpio_soc_defs.h:92
GPP_G2
#define GPP_G2
Definition:
gpio_soc_defs.h:90
GPP_D21
#define GPP_D21
Definition:
gpio_soc_defs.h:131
GPP_G6
#define GPP_G6
Definition:
gpio_soc_defs.h:94
GPP_G0
#define GPP_G0
Definition:
gpio_soc_defs.h:88
GPP_D20
#define GPP_D20
Definition:
gpio_soc_defs.h:130
GPP_G3
#define GPP_G3
Definition:
gpio_soc_defs.h:91
GPP_G5
#define GPP_G5
Definition:
gpio_soc_defs.h:93
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.h:33
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.h:218
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_TERM_GPO
#define PAD_CFG_TERM_GPO(pad, val, pull, rst)
Definition:
gpio_defs.h:262
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_INT
#define PAD_CFG_GPI_INT(pad, pull, rst, trig)
Definition:
gpio_defs.h:348
PAD_CFG_GPI_APIC_HIGH
#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst)
Definition:
gpio_defs.h:405
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_APIC_LOW
#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst)
Definition:
gpio_defs.h:402
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
src
mainboard
google
eve
gpio.h
Generated by
1.9.1