coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mainboard.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
device/pci_ops.h
>
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#include <
southbridge/intel/i82371eb/i82371eb.h
>
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/**
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* Mainboard specific enables.
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*
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* @param chip_info Ignored
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*/
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static
void
mainboard_init
(
void
*chip_info)
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{
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const
pci_devfn_t
px43 =
PCI_DEV
(0, 4, 3);
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u32
reg;
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/*
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* Set up an 8-byte generic I/O decode block at device 9.
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* This will be for W83781D hardware monitor.
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* Port 0x290 mask 0x007
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*
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* This should enable access to W83781D over the ISA bus.
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*/
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reg =
pci_s_read_config32
(px43,
DEVRESB
);
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reg |= (0x290 | (0xe7 << 16));
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pci_s_write_config32
(px43,
DEVRESB
, reg);
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}
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struct
chip_operations
mainboard_ops
= {
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.
init
=
mainboard_init
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};
mainboard_ops
struct chip_operations mainboard_ops
Definition:
mainboard.c:19
mainboard_init
static void mainboard_init(void *chip_info)
Mainboard specific enables.
Definition:
mainboard.c:11
i82371eb.h
DEVRESB
#define DEVRESB
Definition:
i82371eb.h:93
pci_ops.h
pci_s_read_config32
static __always_inline uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
Definition:
pci_io_cfg.h:92
pci_s_write_config32
static __always_inline void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
Definition:
pci_io_cfg.h:110
PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN)
Definition:
pci_type.h:14
pci_devfn_t
u32 pci_devfn_t
Definition:
pci_type.h:8
u32
uint32_t u32
Definition:
stdint.h:51
chip_operations
Definition:
device.h:23
chip_operations::init
void(* init)(void *chip_info)
Definition:
device.h:25
src
mainboard
asus
p2b
mainboard.c
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