coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 
6 /* Pad configuration in ramstage */
7 static const struct pad_config gpio_table[] = {
8  /* A10 : WWAN_EN */
9  PAD_CFG_GPO(GPP_A10, 1, PWROK),
10 
11  /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/
12  PAD_CFG_GPO(GPP_B7, 1, DEEP),
13 
14  /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */
15  PAD_CFG_GPO(GPP_D0, 1, DEEP),
16  /* D22 : AP_I2C_SUB_SDA*/
17  PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
18  /* D23 : AP_I2C_SUB_SCL */
19  PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
20 
21  /* E11 : AP_I2C_SUB_INT_ODL */
22  PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, NONE),
23 
24  /* H17 : WWAN_RST_L */
25  PAD_CFG_GPO(GPP_H17, 0, PLTRST),
26 };
27 
28 const struct pad_config *variant_override_gpio_table(size_t *num)
29 {
30  *num = ARRAY_SIZE(gpio_table);
31  return gpio_table;
32 }
#define GPP_H17
#define GPP_A10
#define GPP_D0
#define GPP_E11
#define GPP_B7
Definition: gpio_soc_defs.h:60
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define GPP_D23
#define GPP_D22
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition: gpio.c:450
static const struct pad_config gpio_table[]
Definition: gpio.c:7
#define PAD_CFG_NF(pad, pull, rst, func)
Definition: gpio_defs.h:197
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition: gpio_defs.h:376
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247