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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Functions | |
void | mux_set_sel (const struct mux *mux, u32 sel) |
static void | pll_calc_values (const struct pll *pll, u32 *pcw, u32 *postdiv, u32 freq) |
static void | pll_set_rate_regs (const struct pll *pll, u32 pcw, u32 postdiv) |
int | pll_set_rate (const struct pll *pll, u32 rate) |
Definition at line 8 of file pll.c.
References mux::clr_reg, GENMASK, mask, mux::mux_shift, mux::mux_width, read32(), mux::reg, mux::set_reg, mux::upd_reg, mux::upd_shift, val, and write32().
Referenced by edp_mux_set_sel(), and mt_pll_init().
Definition at line 26 of file pll.c.
References assert, CLK26M_HZ, pll::div_rate, GHz, PCW_INTEGER_BITS, pll::pcwbits, and val.
Referenced by pll_set_rate().
Definition at line 72 of file pll.c.
References pll_calc_values(), and pll_set_rate_regs().
Referenced by mt_pll_init(), mt_pll_raise_cci_freq(), mt_pll_raise_little_cpu_freq(), and mt_pll_set_tvd_pll1_freq().
Definition at line 49 of file pll.c.
References pll::div_reg, pll::div_shift, GENMASK, pll::pcw_reg, pll::pcw_shift, pll::pcwbits, PLL_POSTDIV_MASK, pll_set_pcw_change(), read32(), val, and write32().
Referenced by pll_set_rate().