coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
pll.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <delay.h>
6 #include <stddef.h>
7 #include <timer.h>
8 
9 #include <soc/addressmap.h>
10 #include <soc/infracfg.h>
11 #include <soc/mcucfg.h>
12 #include <soc/pll.h>
13 #include <soc/spm.h>
14 #include <soc/wdt.h>
15 
16 struct mt8195_infracfg_ao_bcrm_regs {
17  u32 reserved1[13];
18  u32 vdnr_dcm_top_infra_ctrl0; /* 0x0034 */
19 };
20 check_member(mt8195_infracfg_ao_bcrm_regs, vdnr_dcm_top_infra_ctrl0, 0x0034);
21 static struct mt8195_infracfg_ao_bcrm_regs *const mt8195_infracfg_ao_bcrm =
22  (void *)INFRACFG_AO_BCRM_BASE;
23 
24 struct mt8195_pericfg_ao_regs {
25  u32 reserved1[4];
26  u32 peri_module_sw_cg_0_set; /* 0x0010 */
27 };
28 check_member(mt8195_pericfg_ao_regs, peri_module_sw_cg_0_set, 0x0010);
29 static struct mt8195_pericfg_ao_regs *const mt8195_pericfg_ao = (void *)PERICFG_AO_BASE;
30 
31 struct mt8195_scp_adsp_regs {
32  u32 reserved1[96];
33  u32 audiodsp_ck_cg; /* 0x180 */
34 };
35 check_member(mt8195_scp_adsp_regs, audiodsp_ck_cg, 0x0180);
36 static struct mt8195_scp_adsp_regs *const mt8195_scp_adsp =
37  (void *)SCP_ADSP_CFG_BASE;
38 
39 enum mux_id {
40  TOP_AXI_SEL,
41  TOP_SPM_SEL,
42  TOP_SCP_SEL,
43  TOP_BUS_AXIMEM_SEL,
44  TOP_VPP_SEL,
45  TOP_ETHDR_SEL,
46  TOP_IPE_SEL,
47  TOP_CAM_SEL,
48  TOP_CCU_SEL,
49  TOP_IMG_SEL,
50  TOP_CAMTM_SEL,
51  TOP_DSP_SEL,
52  TOP_DSP1_SEL,
53  TOP_DSP2_SEL,
54  TOP_DSP3_SEL,
55  TOP_DSP4_SEL,
56  TOP_DSP5_SEL,
57  TOP_DSP6_SEL,
58  TOP_DSP7_SEL,
59  TOP_IPU_IF_SEL,
60  TOP_MFG_SEL,
61  TOP_CAMTG_SEL,
62  TOP_CAMTG2_SEL,
63  TOP_CAMTG3_SEL,
64  TOP_CAMTG4_SEL,
65  TOP_CAMTG5_SEL,
66  TOP_UART_SEL,
67  TOP_SPI_SEL,
68  TOP_SPIS_SEL,
69  TOP_MSDC50_0_H_SEL,
70  TOP_MSDC50_0_SEL,
71  TOP_MSDC30_1_SEL,
72  TOP_MSDC30_2_SEL,
73  TOP_INTDIR_SEL,
74  TOP_AUD_INTBUS_SEL,
75  TOP_AUDIO_H_SEL,
76  TOP_PWRAP_ULPOSC_SEL,
77  TOP_ATB_SEL,
78  TOP_PWRMCU_SEL,
79  TOP_DP_SEL,
80  TOP_EDP_SEL,
81  TOP_DPI_SEL,
82  TOP_DISP_PWM0_SEL,
83  TOP_DISP_PWM1_SEL,
84  TOP_USB_SEL,
85  TOP_SSUSB_XHCI_SEL,
86  TOP_USB_1P_SEL,
87  TOP_SSUSB_XHCI_1P_SEL,
88  TOP_USB_2P_SEL,
89  TOP_SSUSB_XHCI_2P_SEL,
90  TOP_USB_3P_SEL,
91  TOP_SSUSB_XHCI_3P_SEL,
92  TOP_I2C_SEL,
93  TOP_SENINF_SEL,
94  TOP_SENINF1_SEL,
95  TOP_SENINF2_SEL,
96  TOP_SENINF3_SEL,
97  TOP_GCPU_SEL,
98  TOP_DXCC_SEL,
99  TOP_DPMAIF_SEL,
100  TOP_AES_UFSFDE_SEL,
101  TOP_UFS_SEL,
102  TOP_UFS_TICK1US_SEL,
103  TOP_UFS_MP_SAP_SEL,
104  TOP_VENC_SEL,
105  TOP_VDEC_SEL,
106  TOP_PWM_SEL,
107  TOP_MCUPM_SEL,
108  TOP_SPMI_P_MST_SEL,
109  TOP_SPMI_M_MST_SEL,
110  TOP_DVFSRC_SEL,
111  TOP_TL_SEL,
112  TOP_TL_P1_SEL,
113  TOP_AES_MSDCFDE_SEL,
114  TOP_DSI_OCC_SEL,
115  TOP_WPE_VPP_SEL,
116  TOP_HDCP_SEL,
117  TOP_HDCP_24M_SEL,
118  TOP_HD20_DACR_REF_SEL,
119  TOP_HD20_HDCP_C_SEL,
120  TOP_HDMI_XTAL_SEL,
121  TOP_HDMI_APB_SEL,
122  TOP_SNPS_ETH_250M_SEL,
123  TOP_SNPS_ETH_62P4M_PTP_SEL,
124  TOP_SNPS_ETH_50M_RMII_SEL,
125  TOP_DGI_OUT_SEL,
126  TOP_NNA0_SEL,
127  TOP_NNA1_SEL,
128  TOP_ADSP_SEL,
129  TOP_ASM_H_SEL,
130  TOP_ASM_M_SEL,
131  TOP_ASM_L_SEL,
132  TOP_APLL1_SEL,
133  TOP_APLL2_SEL,
134  TOP_APLL3_SEL,
135  TOP_APLL4_SEL,
136  TOP_APLL5_SEL,
137  TOP_I2SO1_M_SEL,
138  TOP_I2SO2_M_SEL,
139  TOP_I2SI1_M_SEL,
140  TOP_I2SI2_M_SEL,
141  TOP_DPTX_M_SEL,
142  TOP_AUD_IEC_SEL,
143  TOP_A1SYS_HP_SEL,
144  TOP_A2SYS_SEL,
145  TOP_A3SYS_SEL,
146  TOP_A4SYS_SEL,
147  TOP_SPINFI_B_SEL,
148  TOP_NFI1X_SEL,
149  TOP_ECC_SEL,
150  TOP_AUDIO_LOCAL_BUS_SEL,
151  TOP_SPINOR_SEL,
152  TOP_DVIO_DGI_REF_SEL,
153  TOP_SRCK_SEL,
154  TOP_RSVD1_SEL,
155  TOP_MFG_FAST_SEL,
156  TOP_NR_MUX
157 };
158 
159 #define MUX(_id, _reg, _mux_shift, _mux_width) \
160  [_id] = { \
161  .reg = &mtk_topckgen->_reg, \
162  .mux_shift = _mux_shift, \
163  .mux_width = _mux_width, \
164  }
165 
166 #define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
167  [_id] = { \
168  .reg = &mtk_topckgen->_reg, \
169  .set_reg = &mtk_topckgen->_reg##_set, \
170  .clr_reg = &mtk_topckgen->_reg##_clr, \
171  .mux_shift = _mux_shift, \
172  .mux_width = _mux_width, \
173  .upd_reg = &mtk_topckgen->_upd_reg, \
174  .upd_shift = _upd_shift, \
175  }
176 
177 static const struct mux muxes[] = {
178  /* CLK_CFG_0 */
179  MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 3, clk_cfg_update, 0),
180  MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 2, clk_cfg_update, 1),
181  MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2),
182  MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3),
183  /* CLK_CFG_1 */
184  MUX_UPD(TOP_VPP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4),
185  MUX_UPD(TOP_ETHDR_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5),
186  MUX_UPD(TOP_IPE_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6),
187  MUX_UPD(TOP_CAM_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7),
188  /* CLK_CFG_2 */
189  MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8),
190  MUX_UPD(TOP_IMG_SEL, clk_cfg_2, 8, 4, clk_cfg_update, 9),
191  MUX_UPD(TOP_CAMTM_SEL, clk_cfg_2, 16, 2, clk_cfg_update, 10),
192  MUX_UPD(TOP_DSP_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11),
193  /* CLK_CFG_3 */
194  MUX_UPD(TOP_DSP1_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12),
195  MUX_UPD(TOP_DSP2_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13),
196  MUX_UPD(TOP_DSP3_SEL, clk_cfg_3, 16, 3, clk_cfg_update, 14),
197  MUX_UPD(TOP_DSP4_SEL, clk_cfg_3, 24, 3, clk_cfg_update, 15),
198  /* CLK_CFG_4 */
199  MUX_UPD(TOP_DSP5_SEL, clk_cfg_4, 0, 3, clk_cfg_update, 16),
200  MUX_UPD(TOP_DSP6_SEL, clk_cfg_4, 8, 3, clk_cfg_update, 17),
201  MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 16, 3, clk_cfg_update, 18),
202  MUX_UPD(TOP_IPU_IF_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19),
203  /* CLK_CFG_5 */
204  MUX_UPD(TOP_MFG_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20),
205  MUX_UPD(TOP_CAMTG_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21),
206  MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22),
207  MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 24, 3, clk_cfg_update, 23),
208  /* CLK_CFG_6 */
209  MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_6, 0, 3, clk_cfg_update, 24),
210  MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_6, 8, 3, clk_cfg_update, 25),
211  MUX_UPD(TOP_UART_SEL, clk_cfg_6, 16, 1, clk_cfg_update, 26),
212  MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 24, 3, clk_cfg_update, 27),
213  /* CLK_CFG_7 */
214  MUX_UPD(TOP_SPIS_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28),
215  MUX_UPD(TOP_MSDC50_0_H_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29),
216  MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, 16, 3, clk_cfg_update, 30),
217  MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 24, 3, clk_cfg_update, 31),
218  /* CLK_CFG_8 */
219  MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_8, 0, 3, clk_cfg_update1, 0),
220  MUX_UPD(TOP_INTDIR_SEL, clk_cfg_8, 8, 2, clk_cfg_update1, 1),
221  MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 2),
222  MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 3),
223  /* CLK_CFG_9 */
224  MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 4),
225  MUX_UPD(TOP_ATB_SEL, clk_cfg_9, 8, 2, clk_cfg_update1, 5),
226  MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 6),
227  MUX_UPD(TOP_DP_SEL, clk_cfg_9, 24, 4, clk_cfg_update1, 7),
228  /* CLK_CFG_10 */
229  MUX_UPD(TOP_EDP_SEL, clk_cfg_10, 0, 4, clk_cfg_update1, 8),
230  MUX_UPD(TOP_DPI_SEL, clk_cfg_10, 8, 4, clk_cfg_update1, 9),
231  MUX_UPD(TOP_DISP_PWM0_SEL, clk_cfg_10, 16, 3, clk_cfg_update1, 10),
232  MUX_UPD(TOP_DISP_PWM1_SEL, clk_cfg_10, 24, 3, clk_cfg_update1, 11),
233  /* CLK_CFG_11 */
234  MUX_UPD(TOP_USB_SEL, clk_cfg_11, 0, 2, clk_cfg_update1, 12),
235  MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_11, 8, 2, clk_cfg_update1, 13),
236  MUX_UPD(TOP_USB_1P_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 14),
237  MUX_UPD(TOP_SSUSB_XHCI_1P_SEL, clk_cfg_11, 24, 2, clk_cfg_update1, 15),
238  /* CLK_CFG_12 */
239  MUX_UPD(TOP_USB_2P_SEL, clk_cfg_12, 0, 2, clk_cfg_update1, 16),
240  MUX_UPD(TOP_SSUSB_XHCI_2P_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 17),
241  MUX_UPD(TOP_USB_3P_SEL, clk_cfg_12, 16, 2, clk_cfg_update1, 18),
242  MUX_UPD(TOP_SSUSB_XHCI_3P_SEL, clk_cfg_12, 24, 2, clk_cfg_update1, 19),
243  /* CLK_CFG_13 */
244  MUX_UPD(TOP_I2C_SEL, clk_cfg_13, 0, 2, clk_cfg_update1, 20),
245  MUX_UPD(TOP_SENINF_SEL, clk_cfg_13, 8, 3, clk_cfg_update1, 21),
246  MUX_UPD(TOP_SENINF1_SEL, clk_cfg_13, 16, 3, clk_cfg_update1, 22),
247  MUX_UPD(TOP_SENINF2_SEL, clk_cfg_13, 24, 3, clk_cfg_update1, 23),
248  /* CLK_CFG_14 */
249  MUX_UPD(TOP_SENINF3_SEL, clk_cfg_14, 0, 3, clk_cfg_update1, 24),
250  MUX_UPD(TOP_GCPU_SEL, clk_cfg_14, 8, 3, clk_cfg_update1, 25),
251  MUX_UPD(TOP_DXCC_SEL, clk_cfg_14, 16, 2, clk_cfg_update1, 26),
252  MUX_UPD(TOP_DPMAIF_SEL, clk_cfg_14, 24, 3, clk_cfg_update1, 27),
253  /* CLK_CFG_15 */
254  MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_15, 0, 3, clk_cfg_update1, 28),
255  MUX_UPD(TOP_UFS_SEL, clk_cfg_15, 8, 3, clk_cfg_update1, 29),
256  MUX_UPD(TOP_UFS_TICK1US_SEL, clk_cfg_15, 16, 1, clk_cfg_update1, 30),
257  MUX_UPD(TOP_UFS_MP_SAP_SEL, clk_cfg_15, 24, 1, clk_cfg_update1, 31),
258  /* CLK_CFG_16 */
259  MUX_UPD(TOP_VENC_SEL, clk_cfg_16, 0, 4, clk_cfg_update2, 0),
260  MUX_UPD(TOP_VDEC_SEL, clk_cfg_16, 8, 4, clk_cfg_update2, 1),
261  MUX_UPD(TOP_PWM_SEL, clk_cfg_16, 16, 1, clk_cfg_update2, 2),
262  MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, 24, 2, clk_cfg_update2, 3),
263  /* CLK_CFG_17 */
264  MUX_UPD(TOP_SPMI_P_MST_SEL, clk_cfg_17, 0, 4, clk_cfg_update2, 4),
265  MUX_UPD(TOP_SPMI_M_MST_SEL, clk_cfg_17, 8, 4, clk_cfg_update2, 5),
266  MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_17, 16, 2, clk_cfg_update2, 6),
267  MUX_UPD(TOP_TL_SEL, clk_cfg_17, 24, 2, clk_cfg_update2, 7),
268  /* CLK_CFG_18 */
269  MUX_UPD(TOP_TL_P1_SEL, clk_cfg_18, 0, 2, clk_cfg_update2, 8),
270  MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_18, 8, 3, clk_cfg_update2, 9),
271  MUX_UPD(TOP_DSI_OCC_SEL, clk_cfg_18, 16, 2, clk_cfg_update2, 10),
272  MUX_UPD(TOP_WPE_VPP_SEL, clk_cfg_18, 24, 4, clk_cfg_update2, 11),
273  /* CLK_CFG_19 */
274  MUX_UPD(TOP_HDCP_SEL, clk_cfg_19, 0, 2, clk_cfg_update2, 12),
275  MUX_UPD(TOP_HDCP_24M_SEL, clk_cfg_19, 8, 2, clk_cfg_update2, 13),
276  MUX_UPD(TOP_HD20_DACR_REF_SEL, clk_cfg_19, 16, 2, clk_cfg_update2, 14),
277  MUX_UPD(TOP_HD20_HDCP_C_SEL, clk_cfg_19, 24, 2, clk_cfg_update2, 15),
278  /* CLK_CFG_20 */
279  MUX_UPD(TOP_HDMI_XTAL_SEL, clk_cfg_20, 0, 1, clk_cfg_update2, 16),
280  MUX_UPD(TOP_HDMI_APB_SEL, clk_cfg_20, 8, 2, clk_cfg_update2, 17),
281  MUX_UPD(TOP_SNPS_ETH_250M_SEL, clk_cfg_20, 16, 1, clk_cfg_update2, 18),
282  MUX_UPD(TOP_SNPS_ETH_62P4M_PTP_SEL, clk_cfg_20, 24, 2, clk_cfg_update2, 19),
283  /* CLK_CFG_21 */
284  MUX_UPD(TOP_SNPS_ETH_50M_RMII_SEL, clk_cfg_21, 0, 1, clk_cfg_update2, 20),
285  MUX_UPD(TOP_DGI_OUT_SEL, clk_cfg_21, 8, 3, clk_cfg_update2, 21),
286  MUX_UPD(TOP_NNA0_SEL, clk_cfg_21, 16, 4, clk_cfg_update2, 22),
287  MUX_UPD(TOP_NNA1_SEL, clk_cfg_21, 24, 4, clk_cfg_update2, 23),
288  /* CLK_CFG_22 */
289  MUX_UPD(TOP_ADSP_SEL, clk_cfg_22, 0, 4, clk_cfg_update2, 24),
290  MUX_UPD(TOP_ASM_H_SEL, clk_cfg_22, 8, 2, clk_cfg_update2, 25),
291  MUX_UPD(TOP_ASM_M_SEL, clk_cfg_22, 16, 2, clk_cfg_update2, 26),
292  MUX_UPD(TOP_ASM_L_SEL, clk_cfg_22, 24, 2, clk_cfg_update2, 27),
293  /* CLK_CFG_23 */
294  MUX_UPD(TOP_APLL1_SEL, clk_cfg_23, 0, 1, clk_cfg_update2, 28),
295  MUX_UPD(TOP_APLL2_SEL, clk_cfg_23, 8, 1, clk_cfg_update2, 29),
296  MUX_UPD(TOP_APLL3_SEL, clk_cfg_23, 16, 1, clk_cfg_update2, 30),
297  MUX_UPD(TOP_APLL4_SEL, clk_cfg_23, 24, 1, clk_cfg_update2, 31),
298  /* CLK_CFG_24 */
299  MUX_UPD(TOP_APLL5_SEL, clk_cfg_24, 0, 1, clk_cfg_update3, 0),
300  MUX_UPD(TOP_I2SO1_M_SEL, clk_cfg_24, 8, 3, clk_cfg_update3, 1),
301  MUX_UPD(TOP_I2SO2_M_SEL, clk_cfg_24, 16, 3, clk_cfg_update3, 2),
302  /* CLK_CFG_25 */
303  MUX_UPD(TOP_I2SI1_M_SEL, clk_cfg_25, 8, 3, clk_cfg_update3, 5),
304  MUX_UPD(TOP_I2SI2_M_SEL, clk_cfg_25, 16, 3, clk_cfg_update3, 6),
305  /* CLK_CFG_26 */
306  MUX_UPD(TOP_DPTX_M_SEL, clk_cfg_26, 8, 3, clk_cfg_update3, 9),
307  MUX_UPD(TOP_AUD_IEC_SEL, clk_cfg_26, 16, 3, clk_cfg_update3, 10),
308  MUX_UPD(TOP_A1SYS_HP_SEL, clk_cfg_26, 24, 1, clk_cfg_update3, 11),
309  /* CLK_CFG_27 */
310  MUX_UPD(TOP_A2SYS_SEL, clk_cfg_27, 0, 1, clk_cfg_update3, 12),
311  MUX_UPD(TOP_A3SYS_SEL, clk_cfg_27, 8, 3, clk_cfg_update3, 13),
312  MUX_UPD(TOP_A4SYS_SEL, clk_cfg_27, 16, 3, clk_cfg_update3, 14),
313  MUX_UPD(TOP_SPINFI_B_SEL, clk_cfg_27, 24, 3, clk_cfg_update3, 15),
314  /* CLK_CFG_28 */
315  MUX_UPD(TOP_NFI1X_SEL, clk_cfg_28, 0, 3, clk_cfg_update3, 16),
316  MUX_UPD(TOP_ECC_SEL, clk_cfg_28, 8, 3, clk_cfg_update3, 17),
317  MUX_UPD(TOP_AUDIO_LOCAL_BUS_SEL, clk_cfg_28, 16, 4, clk_cfg_update3, 18),
318  MUX_UPD(TOP_SPINOR_SEL, clk_cfg_28, 24, 2, clk_cfg_update3, 19),
319  /* CLK_CFG_29 */
320  MUX_UPD(TOP_DVIO_DGI_REF_SEL, clk_cfg_29, 0, 3, clk_cfg_update3, 20),
321  MUX_UPD(TOP_SRCK_SEL, clk_cfg_29, 24, 1, clk_cfg_update3, 23),
322  /* CLK_CFG_37 */
323  MUX_UPD(TOP_RSVD1_SEL, clk_cfg_37, 0, 3, clk_cfg_update4, 20),
324  /* CLK_MISC_CFG_3 */
325  MUX(TOP_MFG_FAST_SEL, clk_misc_cfg_3, 8, 1),
326 };
327 
328 struct mux_sel {
329  enum mux_id id;
330  u32 sel;
331 };
332 
333 static const struct mux_sel mux_sels[] = {
334  /* CLK_CFG_0 */
335  { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */
336  /* CLK_CFG_37 */
337  { .id = TOP_RSVD1_SEL, .sel = 2 }, /* 2: mainpll_d5_d4 */
338  /* CLK_CFG_0 */
339  { .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */
340  { .id = TOP_SCP_SEL, .sel = 7 }, /* 7: mainpll_d6_d2 */
341  { .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
342  /* CLK_CFG_1 */
343  { .id = TOP_VPP_SEL, .sel = 9 }, /* 9: mainpll_d4 */
344  { .id = TOP_ETHDR_SEL, .sel = 8 }, /* 8: univpll_d6 */
345  { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */
346  { .id = TOP_CAM_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */
347  /* CLK_CFG_2 */
348  { .id = TOP_CCU_SEL, .sel = 2 }, /* 2: mainpll_d4_d2 */
349  { .id = TOP_IMG_SEL, .sel = 11 }, /* 11: univpll_d5_d2 */
350  { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */
351  { .id = TOP_DSP_SEL, .sel = 7 }, /* 7: univpll_d3 */
352  /* CLK_CFG_3 */
353  { .id = TOP_DSP1_SEL, .sel = 7 }, /* 7: univpll_d3 */
354  { .id = TOP_DSP2_SEL, .sel = 7 }, /* 7: univpll_d3 */
355  { .id = TOP_DSP3_SEL, .sel = 7 }, /* 7: univpll_d3 */
356  { .id = TOP_DSP4_SEL, .sel = 7 }, /* 7: univpll_d3 */
357  /* CLK_CFG_4 */
358  { .id = TOP_DSP5_SEL, .sel = 7 }, /* 7: univpll_d3 */
359  { .id = TOP_DSP6_SEL, .sel = 7 }, /* 7: univpll_d3 */
360  { .id = TOP_DSP7_SEL, .sel = 7 }, /* 7: univpll_d3 */
361  { .id = TOP_IPU_IF_SEL, .sel = 7 }, /* 7: mmpll_d4 */
362  /* CLK_CFG_5 */
363  { .id = TOP_MFG_SEL, .sel = 3 }, /* 3: univpll_d7 */
364  { .id = TOP_CAMTG_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
365  { .id = TOP_CAMTG2_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
366  { .id = TOP_CAMTG3_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
367  /* CLK_CFG_6 */
368  { .id = TOP_CAMTG4_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
369  { .id = TOP_CAMTG5_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
370  { .id = TOP_UART_SEL, .sel = 0 }, /* 0: xtal_26m_ck */
371  { .id = TOP_SPI_SEL, .sel = 4 }, /* 4: univpll_d6_d2 */
372  /* CLK_CFG_7 */
373  { .id = TOP_SPIS_SEL, .sel = 1 }, /* 1: univpll_d6 */
374  { .id = TOP_MSDC50_0_H_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
375  { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */
376  { .id = TOP_MSDC30_1_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */
377  /* CLK_CFG_8 */
378  { .id = TOP_MSDC30_2_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */
379  { .id = TOP_INTDIR_SEL, .sel = 3 }, /* 3: univpll_d4 */
380  { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */
381  { .id = TOP_AUDIO_H_SEL, .sel = 2 }, /* 2: apll1_ck */
382  /* CLK_CFG_9 */
383  { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 1 }, /* 1: clk26m */
384  { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
385  { .id = TOP_PWRMCU_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
386  { .id = TOP_DP_SEL, .sel = 3 }, /* 3: tvdpll1_d4 */
387  /* CLK_CFG_10 */
388  { .id = TOP_EDP_SEL, .sel = 3 }, /* 3: tvdpll1_d4 */
389  { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll1_d2 */
390  { .id = TOP_DISP_PWM0_SEL, .sel = 1 }, /* 1: univpll_d6_d4 */
391  { .id = TOP_DISP_PWM1_SEL, .sel = 1 }, /* 1: univpll_d6_d4 */
392  /* CLK_CFG_11 */
393  { .id = TOP_USB_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
394  { .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
395  { .id = TOP_USB_1P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
396  { .id = TOP_SSUSB_XHCI_1P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
397  /* CLK_CFG_12 */
398  { .id = TOP_USB_2P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
399  { .id = TOP_SSUSB_XHCI_2P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
400  { .id = TOP_USB_3P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
401  { .id = TOP_SSUSB_XHCI_3P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
402  /* CLK_CFG_13 */
403  { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */
404  { .id = TOP_SENINF_SEL, .sel = 4 }, /* 4: univpll_d7 */
405  { .id = TOP_SENINF1_SEL, .sel = 4 }, /* 4: univpll_d7 */
406  { .id = TOP_SENINF2_SEL, .sel = 4 }, /* 4: univpll_d7 */
407  /* CLK_CFG_14 */
408  { .id = TOP_SENINF3_SEL, .sel = 4 }, /* 4: univpll_d7 */
409  { .id = TOP_GCPU_SEL, .sel = 3 }, /* 3: mmpll_d5_d2 */
410  { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
411  { .id = TOP_DPMAIF_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */
412  /* CLK_CFG_15 */
413  { .id = TOP_AES_UFSFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */
414  { .id = TOP_UFS_SEL, .sel = 6 }, /* 6: msdcpll_d2 */
415  { .id = TOP_UFS_TICK1US_SEL, .sel = 0 }, /* 0: xtal_26m_d52 */
416  { .id = TOP_UFS_MP_SAP_SEL, .sel = 0 }, /* 0: xtal_26m_ck */
417  /* CLK_CFG_16 */
418  { .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */
419  { .id = TOP_VDEC_SEL, .sel = 1 }, /* 1: mainpll_d5_d2 */
420  { .id = TOP_PWM_SEL, .sel = 1 }, /* 1: univpll_d4_d8 */
421  { .id = TOP_MCUPM_SEL, .sel = 1 }, /* 1: mainpll_d6_d2 */
422  /* CLK_CFG_17 */
423  { .id = TOP_SPMI_P_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */
424  { .id = TOP_SPMI_M_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */
425  { .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: xtal_26m_ck */
426  { .id = TOP_TL_SEL, .sel = 2 }, /* 2: mainpll_d4_d4 */
427  /* CLK_CFG_18 */
428  { .id = TOP_TL_P1_SEL, .sel = 2 }, /* 2: mainpll_d4_d4 */
429  { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */
430  { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: mainpll_d6_d2 */
431  { .id = TOP_WPE_VPP_SEL, .sel = 4 }, /* 4: mainpll_d4_d2 */
432  /* CLK_CFG_19 */
433  { .id = TOP_HDCP_SEL, .sel = 3 }, /* 3: univpll_d6_d4 */
434  { .id = TOP_HDCP_24M_SEL, .sel = 2 }, /* 2: univpll_192m_d8 */
435  { .id = TOP_HD20_DACR_REF_SEL, .sel = 1 }, /* 1: univpll_d4_d2 */
436  { .id = TOP_HD20_HDCP_C_SEL, .sel = 1 }, /* 1: msdcpll_d4 */
437  /* CLK_CFG_20 */
438  { .id = TOP_HDMI_XTAL_SEL, .sel = 0 }, /* 0: xtal_26m_ck */
439  { .id = TOP_HDMI_APB_SEL, .sel = 2 }, /* 2: msdcpll_d2 */
440  { .id = TOP_SNPS_ETH_250M_SEL, .sel = 1 }, /* 1: ethpll_d2 */
441  { .id = TOP_SNPS_ETH_62P4M_PTP_SEL, .sel = 3 }, /* 3: ethpll_d8 */
442  /* CLK_CFG_21 */
443  { .id = TOP_SNPS_ETH_50M_RMII_SEL, .sel = 1 }, /* 1: ethpll_d10 */
444  { .id = TOP_DGI_OUT_SEL, .sel = 5 }, /* 5: mmpll_d4_d4 */
445  { .id = TOP_NNA0_SEL, .sel = 1 }, /* 1: nnapll_ck */
446  { .id = TOP_NNA1_SEL, .sel = 1 }, /* 1: nnapll_ck */
447  /* CLK_CFG_22 */
448  { .id = TOP_ADSP_SEL, .sel = 8 }, /* 8: adsppll_ck */
449  { .id = TOP_ASM_H_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
450  { .id = TOP_ASM_M_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
451  { .id = TOP_ASM_L_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
452  /* CLK_CFG_23 */
453  { .id = TOP_APLL1_SEL, .sel = 1 }, /* 1: apll1_d4 */
454  { .id = TOP_APLL2_SEL, .sel = 1 }, /* 1: apll2_d4 */
455  { .id = TOP_APLL3_SEL, .sel = 1 }, /* 1: apll3_d4 */
456  { .id = TOP_APLL4_SEL, .sel = 1 }, /* 1: apll4_d4 */
457  /* CLK_CFG_24 */
458  { .id = TOP_APLL5_SEL, .sel = 1 }, /* 1: apll5_d4 */
459  { .id = TOP_I2SO1_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
460  { .id = TOP_I2SO2_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
461  /* CLK_CFG_25 */
462  { .id = TOP_I2SI1_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
463  { .id = TOP_I2SI2_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
464  /* CLK_CFG_26 */
465  { .id = TOP_DPTX_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
466  { .id = TOP_AUD_IEC_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
467  { .id = TOP_A1SYS_HP_SEL, .sel = 1 }, /* 1: apll1_d4 */
468  /* CLK_CFG_27 */
469  { .id = TOP_A2SYS_SEL, .sel = 1 }, /* 1: apll2_d4 */
470  { .id = TOP_A3SYS_SEL, .sel = 1 }, /* 1: apll3_d4 */
471  { .id = TOP_A4SYS_SEL, .sel = 2 }, /* 2: apll4_d4 */
472  { .id = TOP_SPINFI_B_SEL, .sel = 7 }, /* 7: univpll_d5_d4 */
473  /* CLK_CFG_28 */
474  { .id = TOP_NFI1X_SEL, .sel = 7 }, /* 7: mainpll_d6_d2 */
475  { .id = TOP_ECC_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */
476  { .id = TOP_AUDIO_LOCAL_BUS_SEL, .sel = 3 }, /* 3: mainpll_d7_d2 */
477  { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d6_d8 */
478  /* CLK_CFG_29 */
479  { .id = TOP_DVIO_DGI_REF_SEL, .sel = 1 }, /* 1: in_dgi_ck */
480  { .id = TOP_SRCK_SEL, .sel = 0 }, /* 0: ulposc_d10 */
481  /* CLK_MISC_CFG_3 */
482  { .id = TOP_MFG_FAST_SEL, .sel = 1 }, /* 1: AD_MFGPLL_OPP_CK */
483 };
484 
485 enum pll_id {
486  APMIXED_ARMPLL_LL,
487  APMIXED_ARMPLL_BL,
488  APMIXED_CCIPLL,
489  APMIXED_NNAPLL,
490  APMIXED_RESPLL,
491  APMIXED_ETHPLL,
492  APMIXED_MSDCPLL,
493  APMIXED_TVDPLL1,
494  APMIXED_TVDPLL2,
495  APMIXED_MMPLL,
496  APMIXED_MAINPLL,
497  APMIXED_VDECPLL,
498  APMIXED_IMGPLL,
499  APMIXED_UNIVPLL,
500  APMIXED_HDMIPLL1,
501  APMIXED_HDMIPLL2,
502  APMIXED_HDMIRX_APLL,
503  APMIXED_USB1PLL,
504  APMIXED_ADSPPLL,
505  APMIXED_APLL1,
506  APMIXED_APLL2,
507  APMIXED_APLL3,
508  APMIXED_APLL4,
509  APMIXED_APLL5,
510  APMIXED_MFGPLL,
511  APMIXED_DGIPLL,
512  APMIXED_PLL_MAX
513 };
514 
515 static const u32 pll_div_rate[] = {
516  3800UL * MHz,
517  1900 * MHz,
518  950 * MHz,
519  475 * MHz,
520  237500 * KHz,
521  0,
522 };
523 
524 static const struct pll plls[] = {
525  PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con4,
526  NO_RSTB_SHIFT, 22, armpll_ll_con2, 24, armpll_ll_con2, 0,
527  pll_div_rate),
528  PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con4,
529  NO_RSTB_SHIFT, 22, armpll_bl_con2, 24, armpll_bl_con2, 0,
530  pll_div_rate),
531  PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con4,
532  NO_RSTB_SHIFT, 22, ccipll_con2, 24, ccipll_con2, 0,
533  pll_div_rate),
534  PLL(APMIXED_NNAPLL, nnapll_con0, nnapll_con4,
535  NO_RSTB_SHIFT, 22, nnapll_con2, 24, nnapll_con2, 0,
536  pll_div_rate),
537  PLL(APMIXED_RESPLL, respll_con0, respll_con4,
538  NO_RSTB_SHIFT, 22, respll_con2, 24, respll_con2, 0,
539  pll_div_rate),
540  PLL(APMIXED_ETHPLL, ethpll_con0, ethpll_con4,
541  NO_RSTB_SHIFT, 22, ethpll_con2, 24, ethpll_con2, 0,
542  pll_div_rate),
543  PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con4,
544  NO_RSTB_SHIFT, 22, msdcpll_con2, 24, msdcpll_con2, 0,
545  pll_div_rate),
546  PLL(APMIXED_TVDPLL1, tvdpll1_con0, tvdpll1_con4,
547  NO_RSTB_SHIFT, 22, tvdpll1_con2, 24, tvdpll1_con2, 0,
548  pll_div_rate),
549  PLL(APMIXED_TVDPLL2, tvdpll2_con0, tvdpll2_con4,
550  NO_RSTB_SHIFT, 22, tvdpll2_con2, 24, tvdpll2_con2, 0,
551  pll_div_rate),
552  PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con4,
553  23, 22, mmpll_con2, 24, mmpll_con2, 0,
554  pll_div_rate),
555  PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con4,
556  23, 22, mainpll_con2, 24, mainpll_con2, 0,
557  pll_div_rate),
558  PLL(APMIXED_VDECPLL, vdecpll_con0, vdecpll_con4,
559  NO_RSTB_SHIFT, 22, vdecpll_con2, 24, vdecpll_con2, 0,
560  pll_div_rate),
561  PLL(APMIXED_IMGPLL, imgpll_con0, imgpll_con4,
562  NO_RSTB_SHIFT, 22, imgpll_con2, 24, imgpll_con2, 0,
563  pll_div_rate),
564  PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con4,
565  23, 22, univpll_con2, 24, univpll_con2, 0,
566  pll_div_rate),
567  PLL(APMIXED_HDMIPLL1, hdmipll1_con0, hdmipll1_con4,
568  NO_RSTB_SHIFT, 22, hdmipll1_con2, 24, hdmipll1_con2, 0,
569  pll_div_rate),
570  PLL(APMIXED_HDMIPLL2, hdmipll2_con0, hdmipll2_con4,
571  NO_RSTB_SHIFT, 22, hdmipll2_con2, 24, hdmipll2_con2, 0,
572  pll_div_rate),
573  PLL(APMIXED_HDMIRX_APLL, hdmirx_apll_con0, hdmirx_apll_con5,
574  NO_RSTB_SHIFT, 32, hdmirx_apll_con2, 24, hdmirx_apll_con3, 0,
575  pll_div_rate),
576  PLL(APMIXED_USB1PLL, usb1pll_con0, usb1pll_con4,
577  NO_RSTB_SHIFT, 22, usb1pll_con2, 24, usb1pll_con2, 0,
578  pll_div_rate),
579  PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con4,
580  NO_RSTB_SHIFT, 22, adsppll_con2, 24, adsppll_con2, 0,
581  pll_div_rate),
582  PLL(APMIXED_APLL1, apll1_con0, apll1_con5,
583  NO_RSTB_SHIFT, 32, apll1_con2, 24, apll1_con3, 0,
584  pll_div_rate),
585  PLL(APMIXED_APLL2, apll2_con0, apll2_con5,
586  NO_RSTB_SHIFT, 32, apll2_con2, 24, apll2_con3, 0,
587  pll_div_rate),
588  PLL(APMIXED_APLL3, apll3_con0, apll3_con5,
589  NO_RSTB_SHIFT, 32, apll3_con2, 24, apll3_con3, 0,
590  pll_div_rate),
591  PLL(APMIXED_APLL4, apll4_con0, apll4_con5,
592  NO_RSTB_SHIFT, 32, apll4_con2, 24, apll4_con3, 0,
593  pll_div_rate),
594  PLL(APMIXED_APLL5, apll5_con0, apll5_con5,
595  NO_RSTB_SHIFT, 32, apll5_con2, 24, apll5_con3, 0,
596  pll_div_rate),
597  PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con4,
598  NO_RSTB_SHIFT, 22, mfgpll_con2, 24, mfgpll_con2, 0,
599  pll_div_rate),
600  PLL(APMIXED_DGIPLL, dgipll_con0, dgipll_con4,
601  NO_RSTB_SHIFT, 22, dgipll_con2, 24, dgipll_con2, 0,
602  pll_div_rate),
603 };
604 
605 struct rate {
606  enum pll_id id;
607  u32 rate;
608 };
609 
610 static const struct rate rates[] = {
611  { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ },
612  { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ },
613  { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ },
614  { .id = APMIXED_NNAPLL, .rate = NNAPLL_HZ },
615  { .id = APMIXED_RESPLL, .rate = RESPLL_HZ },
616  { .id = APMIXED_ETHPLL, .rate = ETHPLL_HZ },
617  { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
618  { .id = APMIXED_TVDPLL1, .rate = TVDPLL1_HZ },
619  { .id = APMIXED_TVDPLL2, .rate = TVDPLL2_HZ },
620  { .id = APMIXED_MMPLL, .rate = MMPLL_HZ },
621  { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ },
622  { .id = APMIXED_VDECPLL, .rate = VDECPLL_HZ },
623  { .id = APMIXED_IMGPLL, .rate = IMGPLL_HZ },
624  { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ },
625  { .id = APMIXED_HDMIPLL1, .rate = HDMIPLL1_HZ },
626  { .id = APMIXED_HDMIPLL2, .rate = HDMIPLL2_HZ },
627  { .id = APMIXED_HDMIRX_APLL, .rate = HDMIRX_APLL_HZ },
628  { .id = APMIXED_USB1PLL, .rate = USB1PLL_HZ },
629  { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ },
630  { .id = APMIXED_APLL1, .rate = APLL1_HZ },
631  { .id = APMIXED_APLL2, .rate = APLL2_HZ },
632  { .id = APMIXED_APLL3, .rate = APLL3_HZ },
633  { .id = APMIXED_APLL4, .rate = APLL4_HZ },
634  { .id = APMIXED_APLL5, .rate = APLL5_HZ },
635  { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ },
636  { .id = APMIXED_DGIPLL, .rate = DGIPLL_HZ },
637 };
638 
639 void pll_set_pcw_change(const struct pll *pll)
640 {
641  setbits32(pll->div_reg, PLL_PCW_CHG);
642 }
643 
644 void mt_pll_init(void)
645 {
646  int i;
647 
648  /* enable clock square */
649  setbits32(&mtk_apmixed->ap_pll_con0, BIT(2));
650 
651  udelay(PLL_CKSQ_ON_DELAY);
652 
653  /* enable clock square1 low-pass filter */
654  setbits32(&mtk_apmixed->ap_pll_con0, BIT(1));
655 
656  /*
657  * BIT(3): 1 for register control; 0 for sleep control
658  * BIT(8): 1 to enable clock square2; 0 to disable it
659  */
660  clrbits32(&mtk_apmixed->ap_pll_con0, BIT(3) | BIT(8));
661 
662  /* xPLL PWR ON */
663  for (i = 0; i < APMIXED_PLL_MAX; i++)
664  setbits32(plls[i].pwr_reg, PLL_PWR_ON);
665 
666  udelay(PLL_PWR_ON_DELAY);
667 
668  /* xPLL ISO Disable */
669  for (i = 0; i < APMIXED_PLL_MAX; i++)
670  clrbits32(plls[i].pwr_reg, PLL_ISO);
671 
672  udelay(PLL_ISO_DELAY);
673 
674  /* disable glitch free if rate < 374MHz */
675  for (i = 0; i < ARRAY_SIZE(rates); i++) {
676  if (rates[i].rate < 374 * MHz)
677  clrbits32(plls[rates[i].id].reg, GLITCH_FREE_EN);
678  }
679 
680  /* disable mfg_ck_en[20], enable mfg_opp_ck_en[2] */
681  clrbits32(&mtk_apmixed->mfgpll_con0, 0x1 << 20);
682  setbits32(&mtk_apmixed->mfgpll_con1, 0x1 << 2);
683 
684  /* xPLL Frequency Set */
685  for (i = 0; i < ARRAY_SIZE(rates); i++)
686  pll_set_rate(&plls[rates[i].id], rates[i].rate);
687 
688  /* AUDPLL Tuner Frequency Set */
689  write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con3) + 1);
690  write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con3) + 1);
691  write32(&mtk_apmixed->apll3_tuner_con0, read32(&mtk_apmixed->apll3_con3) + 1);
692  write32(&mtk_apmixed->apll4_tuner_con0, read32(&mtk_apmixed->apll4_con3) + 1);
693  write32(&mtk_apmixed->apll5_tuner_con0, read32(&mtk_apmixed->apll5_con3) + 1);
694 
695  /* xPLL Frequency Enable */
696  for (i = 0; i < APMIXED_PLL_MAX; i++) {
697  if (i == APMIXED_APLL5)
698  setbits32(plls[i].pwr_reg, MT8195_APLL5_EN);
699  else
700  setbits32(plls[i].reg, MT8195_PLL_EN);
701  }
702 
703  /* enable univpll analog divider=13 */
704  setbits32(&mtk_apmixed->univpll_con0, 0x8d);
705 
706  /* wait for PLL stable */
707  udelay(PLL_EN_DELAY);
708 
709  /* xPLL DIV Enable & RSTB */
710  for (i = 0; i < APMIXED_PLL_MAX; i++) {
711  if (plls[i].rstb_shift != NO_RSTB_SHIFT) {
712  setbits32(plls[i].reg, PLL_DIV_EN);
713  setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
714  }
715  }
716 
717  /* MCUCFG CLKMUX */
718  clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
719  clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
720  clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
721 
722  clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
723  clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
724  clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
725 
726  /* enable infrasys DCM */
727  setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21);
728  setbits32(&mt8195_infracfg_ao_bcrm->vdnr_dcm_top_infra_ctrl0, 0x2);
729 
730  /* dcm_infracfg_ao_aximem_bus_dcm */
731  clrsetbits32(&mt8195_infracfg_ao->infra_aximem_idle_bit_en_0,
732  INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK,
733  INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON);
734  /* dcm_infracfg_ao_infra_bus_dcm */
735  clrsetbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl,
736  INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK,
737  INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
738  /* dcm_infracfg_ao_infra_rx_p2p_dcm */
739  clrsetbits32(&mt8195_infracfg_ao->p2p_rx_clk_on,
740  INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK,
741  INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON);
742  /* dcm_infracfg_ao_peri_bus_dcm */
743  clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl,
744  INFRACFG_AO_PERI_BUS_DCM_REG0_MASK,
745  INFRACFG_AO_PERI_BUS_DCM_REG0_ON);
746  /* dcm_infracfg_ao_peri_module_dcm */
747  clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl,
748  INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK,
749  INFRACFG_AO_PERI_MODULE_DCM_REG0_ON);
750 
751  /* initialize SPM request */
752  setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff);
753 
754  /*
755  * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
756  */
757  for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
758  mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
759 
760  /* switch sram control to bypass mode for PCIE_MAC_P0 */
761  setbits32(&mtk_spm->ap_mdsrc_req, 0x1);
762 
763  /* ctitical clock */
764  write32(&mt8195_infracfg_ao->module_sw_cg_0_clr, 0x00000020);
765  write32(&mt8195_infracfg_ao->module_sw_cg_1_clr, 0x00100000);
766  write32(&mt8195_infracfg_ao->module_sw_cg_2_clr, 0x02000000);
767  write32(&mt8195_infracfg_ao->module_sw_cg_3_clr, 0x00000003);
768 
769  /* turn off unused clock */
770  write32(&mt8195_pericfg_ao->peri_module_sw_cg_0_set, 0x10);
771 
772  /* scp_dsp for audio */
773  clrbits32(&mt8195_scp_adsp->audiodsp_ck_cg, BIT(0));
774 
775  /* audio 26M */
776  setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(4));
777 }
778 
779 void mt_pll_raise_little_cpu_freq(u32 freq)
780 {
781  /* switch clock source to intermediate clock */
782  clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M);
783 
784  /* disable armpll_ll frequency output */
785  clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN);
786 
787  /* raise armpll_ll frequency */
788  pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
789 
790  /* enable armpll_ll frequency output */
791  setbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN);
792  udelay(PLL_EN_DELAY);
793 
794  /* switch clock source back to armpll_ll */
795  clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
796 }
797 
798 void mt_pll_raise_cci_freq(u32 freq)
799 {
800  /* switch clock source to intermediate clock */
801  clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M);
802 
803  /* disable ccipll frequency output */
804  clrbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN);
805 
806  /* raise ccipll frequency */
807  pll_set_rate(&plls[APMIXED_CCIPLL], freq);
808 
809  /* enable ccipll frequency output */
810  setbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN);
811  udelay(PLL_EN_DELAY);
812 
813  /* switch clock source back to ccipll */
814  clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
815 }
816 
817 void mt_pll_set_tvd_pll1_freq(u32 freq)
818 {
819  /* disable tvdpll frequency output */
820  clrbits32(plls[APMIXED_TVDPLL1].reg, MT8195_PLL_EN);
821 
822  /* set tvdpll frequency */
823  pll_set_rate(&plls[APMIXED_TVDPLL1], freq);
824 
825  /* enable tvdpll frequency output */
826  setbits32(plls[APMIXED_TVDPLL1].reg, MT8195_PLL_EN);
827  udelay(PLL_EN_DELAY);
828 }
829 
830 void edp_mux_set_sel(u32 sel)
831 {
832  mux_set_sel(&muxes[TOP_EDP_SEL], sel);
833 }
834 
835 u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
836 {
837  u32 output, count, clk_dbg_cfg, clk_misc_cfg_0;
838 
839  /* backup */
840  clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg);
841  clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0);
842 
843  /* set up frequency meter */
844  if (type == FMETER_ABIST) {
845  SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
846  CLK_DBG_CFG_ABIST_CK_SEL, id,
847  CLK_DBG_CFG_CKGEN_CK_SEL, 0,
848  CLK_DBG_CFG_METER_CK_SEL, 0,
849  CLK_DBG_CFG_CKGEN_EN, 0);
850  SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
851  CLK_MISC_CFG_0_METER_DIV, 3);
852  } else if (type == FMETER_CKGEN) {
853  SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
854  CLK_DBG_CFG_ABIST_CK_SEL, 0,
855  CLK_DBG_CFG_CKGEN_CK_SEL, id,
856  CLK_DBG_CFG_METER_CK_SEL, 1,
857  CLK_DBG_CFG_CKGEN_EN, 1);
858  SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
859  CLK_MISC_CFG_0_METER_DIV, 0);
860  } else {
861  die("unsupported fmeter type\n");
862  }
863 
864  /* enable frequency meter */
865  write32(&mtk_topckgen->clk26cali_0, 0x80);
866 
867  /* set load count = 1024-1 */
868  SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, CLK26CALI_1_LOAD_CNT, 0x3ff);
869 
870  /* trigger frequency meter */
871  SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1);
872 
873  /* wait frequency meter until finished */
874  if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) {
875  count = read32(&mtk_topckgen->clk26cali_1) & 0xffff;
876  output = (count * 26000) / 1024; /* KHz */
877  } else {
878  printk(BIOS_WARNING, "fmeter timeout\n");
879  output = 0;
880  }
881 
882  /* disable frequency meter */
883  write32(&mtk_topckgen->clk26cali_0, 0x0000);
884 
885  /* restore */
886  write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg);
887  write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0);
888 
889  if (type == FMETER_ABIST)
890  return output * 4;
891  else if (type == FMETER_CKGEN)
892  return output;
893 
894  return 0;
895 }
write32
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
read32
static uint32_t read32(const void *addr)
Definition: mmio.h:22
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition: helpers.h:12
MHz
#define MHz
Definition: helpers.h:80
KHz
#define KHz
Definition: helpers.h:79
mux_set_sel
void mux_set_sel(const struct mux *mux, u32 sel)
Definition: pll.c:8
pll_set_rate
int pll_set_rate(const struct pll *pll, u32 rate)
Definition: pll.c:72
printk
#define printk(level,...)
Definition: stdlib.h:16
die
void __noreturn die(const char *fmt,...)
Definition: die.c:17
BIT
#define BIT(nr)
Definition: ec_commands.h:45
setbits32
#define setbits32(addr, set)
Definition: mmio.h:21
SET32_BITFIELDS
#define SET32_BITFIELDS(addr,...)
Definition: mmio.h:201
READ32_BITFIELD
#define READ32_BITFIELD(addr, name)
Definition: mmio.h:207
clrsetbits32
#define clrsetbits32(addr, clear, set)
Definition: mmio.h:16
clrbits32
#define clrbits32(addr, clear)
Definition: mmio.h:26
wait_us
#define wait_us(timeout_us, condition)
Definition: timer.h:198
type
unsigned int type
Definition: edid.c:57
BIOS_WARNING
#define BIOS_WARNING
BIOS_WARNING - Bad configuration.
Definition: loglevel.h:86
UNIVPLL_HZ
@ UNIVPLL_HZ
Definition: pll.h:196
MSDCPLL_HZ
@ MSDCPLL_HZ
Definition: pll.h:198
MAINPLL_HZ
@ MAINPLL_HZ
Definition: pll.h:195
MMPLL_HZ
@ MMPLL_HZ
Definition: pll.h:197
APLL1_HZ
@ APLL1_HZ
Definition: pll.h:205
APLL2_HZ
@ APLL2_HZ
Definition: pll.h:206
PLL_ISO_DELAY
@ PLL_ISO_DELAY
Definition: pll.h:183
PLL_EN_DELAY
@ PLL_EN_DELAY
Definition: pll.h:184
PLL_PWR_ON_DELAY
@ PLL_PWR_ON_DELAY
Definition: pll.h:182
mtk_spm
static struct mtk_spm_regs *const mtk_spm
Definition: spm.h:154
mt_pll_init
void mt_pll_init(void)
Definition: pll.c:289
pll_id
pll_id
Definition: pll.c:172
APMIXED_MMPLL
@ APMIXED_MMPLL
Definition: pll.c:177
APMIXED_APLL1
@ APMIXED_APLL1
Definition: pll.c:183
APMIXED_UNIVPLL
@ APMIXED_UNIVPLL
Definition: pll.c:176
APMIXED_APLL2
@ APMIXED_APLL2
Definition: pll.c:184
APMIXED_MSDCPLL
@ APMIXED_MSDCPLL
Definition: pll.c:178
APMIXED_MAINPLL
@ APMIXED_MAINPLL
Definition: pll.c:175
pll_div_rate
const u32 pll_div_rate[]
Definition: pll.c:190
mt_pll_raise_little_cpu_freq
void mt_pll_raise_little_cpu_freq(u32 freq)
Definition: pll.c:420
pll_set_pcw_change
void pll_set_pcw_change(const struct pll *pll)
Definition: pll.c:284
mux_id
mux_id
Definition: pll.c:11
TOP_VENC_SEL
@ TOP_VENC_SEL
Definition: pll.c:18
TOP_MSDC50_0_SEL
@ TOP_MSDC50_0_SEL
Definition: pll.c:26
TOP_MSDC50_0_H_SEL
@ TOP_MSDC50_0_H_SEL
Definition: pll.c:25
TOP_AUD_INTBUS_SEL
@ TOP_AUD_INTBUS_SEL
Definition: pll.c:31
TOP_UART_SEL
@ TOP_UART_SEL
Definition: pll.c:21
TOP_ATB_SEL
@ TOP_ATB_SEL
Definition: pll.c:34
TOP_MFG_SEL
@ TOP_MFG_SEL
Definition: pll.c:19
TOP_MSDC30_1_SEL
@ TOP_MSDC30_1_SEL
Definition: pll.c:27
TOP_MSDC30_2_SEL
@ TOP_MSDC30_2_SEL
Definition: pll.c:28
TOP_SCP_SEL
@ TOP_SCP_SEL
Definition: pll.c:33
TOP_HDCP_24M_SEL
@ TOP_HDCP_24M_SEL
Definition: pll.c:49
TOP_HDCP_SEL
@ TOP_HDCP_SEL
Definition: pll.c:48
TOP_CAMTG_SEL
@ TOP_CAMTG_SEL
Definition: pll.c:20
TOP_SPI_SEL
@ TOP_SPI_SEL
Definition: pll.c:22
TOP_PWM_SEL
@ TOP_PWM_SEL
Definition: pll.c:16
TOP_NR_MUX
@ TOP_NR_MUX
Definition: pll.c:51
TOP_VDEC_SEL
@ TOP_VDEC_SEL
Definition: pll.c:17
TOP_AXI_SEL
@ TOP_AXI_SEL
Definition: pll.c:12
CCIPLL_HZ
@ CCIPLL_HZ
Definition: pll.h:237
MFGPLL_HZ
@ MFGPLL_HZ
Definition: pll.h:242
ARMPLL_LL_HZ
@ ARMPLL_LL_HZ
Definition: pll.h:235
APMIXED_PLL_MAX
@ APMIXED_PLL_MAX
Definition: pll.c:198
APMIXED_ARMPLL_LL
@ APMIXED_ARMPLL_LL
Definition: pll.c:186
APMIXED_CCIPLL
@ APMIXED_CCIPLL
Definition: pll.c:188
APMIXED_MFGPLL
@ APMIXED_MFGPLL
Definition: pll.c:193
TOP_AES_UFSFDE_SEL
@ TOP_AES_UFSFDE_SEL
Definition: pll.c:50
TOP_SENINF_SEL
@ TOP_SENINF_SEL
Definition: pll.c:46
TOP_PWRMCU_SEL
@ TOP_PWRMCU_SEL
Definition: pll.c:37
TOP_CAMTG2_SEL
@ TOP_CAMTG2_SEL
Definition: pll.c:23
TOP_DSP_SEL
@ TOP_DSP_SEL
Definition: pll.c:16
TOP_UFS_SEL
@ TOP_UFS_SEL
Definition: pll.c:51
TOP_I2C_SEL
@ TOP_I2C_SEL
Definition: pll.c:44
TOP_IMG_SEL
@ TOP_IMG_SEL
Definition: pll.c:14
TOP_DSP2_SEL
@ TOP_DSP2_SEL
Definition: pll.c:18
TOP_SSUSB_XHCI_SEL
@ TOP_SSUSB_XHCI_SEL
Definition: pll.c:42
TOP_CAMTG4_SEL
@ TOP_CAMTG4_SEL
Definition: pll.c:25
TOP_CAMTG3_SEL
@ TOP_CAMTG3_SEL
Definition: pll.c:24
TOP_SPM_SEL
@ TOP_SPM_SEL
Definition: pll.c:43
TOP_PWRAP_ULPOSC_SEL
@ TOP_PWRAP_ULPOSC_SEL
Definition: pll.c:35
TOP_IPU_IF_SEL
@ TOP_IPU_IF_SEL
Definition: pll.c:19
TOP_DXCC_SEL
@ TOP_DXCC_SEL
Definition: pll.c:47
TOP_CAM_SEL
@ TOP_CAM_SEL
Definition: pll.c:15
TOP_DSP1_SEL
@ TOP_DSP1_SEL
Definition: pll.c:17
mtk_mcucfg
static struct mt8186_mcucfg_regs *const mtk_mcucfg
Definition: mcucfg.h:945
NNAPLL_HZ
@ NNAPLL_HZ
Definition: pll.h:483
ARMPLL_BL_HZ
@ ARMPLL_BL_HZ
Definition: pll.h:477
ADSPPLL_HZ
@ ADSPPLL_HZ
Definition: pll.h:485
PLL_CKSQ_ON_DELAY
@ PLL_CKSQ_ON_DELAY
Definition: pll.h:444
GLITCH_FREE_EN
@ GLITCH_FREE_EN
Definition: pll.h:456
PLL_DIV_EN
@ PLL_DIV_EN
Definition: pll.h:457
MCU_MUX_MASK
@ MCU_MUX_MASK
Definition: pll.h:469
MCU_DIV_MASK
@ MCU_DIV_MASK
Definition: pll.h:466
MCU_DIV_1
@ MCU_DIV_1
Definition: pll.h:467
MCU_MUX_SRC_PLL
@ MCU_MUX_SRC_PLL
Definition: pll.h:470
MCU_MUX_SRC_26M
@ MCU_MUX_SRC_26M
Definition: pll.h:471
APMIXED_NNAPLL
@ APMIXED_NNAPLL
Definition: pll.c:280
APMIXED_ARMPLL_BL
@ APMIXED_ARMPLL_BL
Definition: pll.c:274
APMIXED_ADSPPLL
@ APMIXED_ADSPPLL
Definition: pll.c:282
mt_fmeter_get_freq_khz
u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
Definition: pll.c:519
mt_pll_raise_cci_freq
void mt_pll_raise_cci_freq(u32 freq)
Definition: pll.c:500
TOP_DVFSRC_SEL
@ TOP_DVFSRC_SEL
Definition: pll.c:68
TOP_SENINF1_SEL
@ TOP_SENINF1_SEL
Definition: pll.c:50
TOP_CAMTM_SEL
@ TOP_CAMTM_SEL
Definition: pll.c:55
TOP_SENINF3_SEL
@ TOP_SENINF3_SEL
Definition: pll.c:52
TOP_SPINOR_SEL
@ TOP_SPINOR_SEL
Definition: pll.c:71
TOP_DSI_OCC_SEL
@ TOP_DSI_OCC_SEL
Definition: pll.c:69
TOP_IPE_SEL
@ TOP_IPE_SEL
Definition: pll.c:59
TOP_SRCK_SEL
@ TOP_SRCK_SEL
Definition: pll.c:45
TOP_AES_MSDCFDE_SEL
@ TOP_AES_MSDCFDE_SEL
Definition: pll.c:53
TOP_DPI_SEL
@ TOP_DPI_SEL
Definition: pll.c:80
TOP_DPMAIF_SEL
@ TOP_DPMAIF_SEL
Definition: pll.c:60
TOP_SENINF2_SEL
@ TOP_SENINF2_SEL
Definition: pll.c:51
TOP_NNA1_SEL
@ TOP_NNA1_SEL
Definition: pll.c:73
TOP_SSUSB_XHCI_1P_SEL
@ TOP_SSUSB_XHCI_1P_SEL
Definition: pll.c:77
TOP_CAMTG5_SEL
@ TOP_CAMTG5_SEL
Definition: pll.c:28
TOP_AUDIO_H_SEL
@ TOP_AUDIO_H_SEL
Definition: pll.c:64
INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK
@ INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK
Definition: pll.h:321
INFRACFG_AO_PERI_BUS_DCM_REG0_ON
@ INFRACFG_AO_PERI_BUS_DCM_REG0_ON
Definition: pll.h:356
INFRACFG_AO_PERI_BUS_DCM_REG0_MASK
@ INFRACFG_AO_PERI_BUS_DCM_REG0_MASK
Definition: pll.h:347
INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON
@ INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON
Definition: pll.h:346
INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK
@ INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK
Definition: pll.h:323
INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK
@ INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK
Definition: pll.h:345
INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK
@ INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK
Definition: pll.h:365
INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON
@ INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON
Definition: pll.h:322
INFRACFG_AO_INFRA_BUS_DCM_REG0_ON
@ INFRACFG_AO_INFRA_BUS_DCM_REG0_ON
Definition: pll.h:332
INFRACFG_AO_PERI_MODULE_DCM_REG0_ON
@ INFRACFG_AO_PERI_MODULE_DCM_REG0_ON
Definition: pll.h:366
TOP_MCUPM_SEL
@ TOP_MCUPM_SEL
Definition: pll.c:77
TOP_DSP7_SEL
@ TOP_DSP7_SEL
Definition: pll.c:29
TOP_ADSP_SEL
@ TOP_ADSP_SEL
Definition: pll.c:67
TOP_TL_SEL
@ TOP_TL_SEL
Definition: pll.c:59
TOP_BUS_AXIMEM_SEL
@ TOP_BUS_AXIMEM_SEL
Definition: pll.c:19
TOP_CCU_SEL
@ TOP_CCU_SEL
Definition: pll.c:27
mt8195_infracfg_ao
static struct mt8195_infracfg_ao_regs *const mt8195_infracfg_ao
Definition: infracfg.h:409
RESPLL_HZ
@ RESPLL_HZ
Definition: pll.h:539
HDMIRX_APLL_HZ
@ HDMIRX_APLL_HZ
Definition: pll.h:551
ETHPLL_HZ
@ ETHPLL_HZ
Definition: pll.h:540
TVDPLL1_HZ
@ TVDPLL1_HZ
Definition: pll.h:542
APLL5_HZ
@ APLL5_HZ
Definition: pll.h:558
IMGPLL_HZ
@ IMGPLL_HZ
Definition: pll.h:547
APLL3_HZ
@ APLL3_HZ
Definition: pll.h:556
VDECPLL_HZ
@ VDECPLL_HZ
Definition: pll.h:546
USB1PLL_HZ
@ USB1PLL_HZ
Definition: pll.h:552
TVDPLL2_HZ
@ TVDPLL2_HZ
Definition: pll.h:543
APLL4_HZ
@ APLL4_HZ
Definition: pll.h:557
HDMIPLL2_HZ
@ HDMIPLL2_HZ
Definition: pll.h:550
HDMIPLL1_HZ
@ HDMIPLL1_HZ
Definition: pll.h:549
DGIPLL_HZ
@ DGIPLL_HZ
Definition: pll.h:560
MT8195_PLL_EN
@ MT8195_PLL_EN
Definition: pll.h:518
MT8195_APLL5_EN
@ MT8195_APLL5_EN
Definition: pll.h:519
mt8195_infracfg_ao_bcrm
static struct mt8195_infracfg_ao_bcrm_regs *const mt8195_infracfg_ao_bcrm
Definition: pll.c:21
muxes
static const struct mux muxes[]
Definition: pll.c:177
APMIXED_TVDPLL1
@ APMIXED_TVDPLL1
Definition: pll.c:493
APMIXED_HDMIRX_APLL
@ APMIXED_HDMIRX_APLL
Definition: pll.c:502
APMIXED_HDMIPLL1
@ APMIXED_HDMIPLL1
Definition: pll.c:500
APMIXED_VDECPLL
@ APMIXED_VDECPLL
Definition: pll.c:497
APMIXED_APLL5
@ APMIXED_APLL5
Definition: pll.c:509
APMIXED_APLL4
@ APMIXED_APLL4
Definition: pll.c:508
APMIXED_HDMIPLL2
@ APMIXED_HDMIPLL2
Definition: pll.c:501
APMIXED_ETHPLL
@ APMIXED_ETHPLL
Definition: pll.c:491
APMIXED_TVDPLL2
@ APMIXED_TVDPLL2
Definition: pll.c:494
APMIXED_APLL3
@ APMIXED_APLL3
Definition: pll.c:507
APMIXED_USB1PLL
@ APMIXED_USB1PLL
Definition: pll.c:503
APMIXED_DGIPLL
@ APMIXED_DGIPLL
Definition: pll.c:511
APMIXED_RESPLL
@ APMIXED_RESPLL
Definition: pll.c:490
APMIXED_IMGPLL
@ APMIXED_IMGPLL
Definition: pll.c:498
edp_mux_set_sel
void edp_mux_set_sel(u32 sel)
Definition: pll.c:830
rates
static const struct rate rates[]
Definition: pll.c:610
MUX_UPD
#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)
Definition: pll.c:166
MUX
#define MUX(_id, _reg, _mux_shift, _mux_width)
Definition: pll.c:159
mux_sels
static const struct mux_sel mux_sels[]
Definition: pll.c:333
mt8195_pericfg_ao
static struct mt8195_pericfg_ao_regs *const mt8195_pericfg_ao
Definition: pll.c:29
mt8195_scp_adsp
static struct mt8195_scp_adsp_regs *const mt8195_scp_adsp
Definition: pll.c:36
check_member
check_member(mt8195_infracfg_ao_bcrm_regs, vdnr_dcm_top_infra_ctrl0, 0x0034)
plls
static const struct pll plls[]
Definition: pll.c:524
TOP_MFG_FAST_SEL
@ TOP_MFG_FAST_SEL
Definition: pll.c:155
TOP_A3SYS_SEL
@ TOP_A3SYS_SEL
Definition: pll.c:145
TOP_SPMI_P_MST_SEL
@ TOP_SPMI_P_MST_SEL
Definition: pll.c:108
TOP_USB_2P_SEL
@ TOP_USB_2P_SEL
Definition: pll.c:88
TOP_SNPS_ETH_62P4M_PTP_SEL
@ TOP_SNPS_ETH_62P4M_PTP_SEL
Definition: pll.c:123
TOP_SSUSB_XHCI_3P_SEL
@ TOP_SSUSB_XHCI_3P_SEL
Definition: pll.c:91
TOP_APLL2_SEL
@ TOP_APLL2_SEL
Definition: pll.c:133
TOP_UFS_TICK1US_SEL
@ TOP_UFS_TICK1US_SEL
Definition: pll.c:102
TOP_DVIO_DGI_REF_SEL
@ TOP_DVIO_DGI_REF_SEL
Definition: pll.c:152
TOP_A1SYS_HP_SEL
@ TOP_A1SYS_HP_SEL
Definition: pll.c:143
TOP_APLL1_SEL
@ TOP_APLL1_SEL
Definition: pll.c:132
TOP_RSVD1_SEL
@ TOP_RSVD1_SEL
Definition: pll.c:154
TOP_UFS_MP_SAP_SEL
@ TOP_UFS_MP_SAP_SEL
Definition: pll.c:103
TOP_USB_SEL
@ TOP_USB_SEL
Definition: pll.c:84
TOP_EDP_SEL
@ TOP_EDP_SEL
Definition: pll.c:80
TOP_I2SI2_M_SEL
@ TOP_I2SI2_M_SEL
Definition: pll.c:140
TOP_ASM_H_SEL
@ TOP_ASM_H_SEL
Definition: pll.c:129
TOP_APLL4_SEL
@ TOP_APLL4_SEL
Definition: pll.c:135
TOP_ETHDR_SEL
@ TOP_ETHDR_SEL
Definition: pll.c:45
TOP_DSP3_SEL
@ TOP_DSP3_SEL
Definition: pll.c:54
TOP_SNPS_ETH_50M_RMII_SEL
@ TOP_SNPS_ETH_50M_RMII_SEL
Definition: pll.c:124
TOP_SNPS_ETH_250M_SEL
@ TOP_SNPS_ETH_250M_SEL
Definition: pll.c:122
TOP_GCPU_SEL
@ TOP_GCPU_SEL
Definition: pll.c:97
TOP_APLL5_SEL
@ TOP_APLL5_SEL
Definition: pll.c:136
TOP_DP_SEL
@ TOP_DP_SEL
Definition: pll.c:79
TOP_A2SYS_SEL
@ TOP_A2SYS_SEL
Definition: pll.c:144
TOP_HDMI_APB_SEL
@ TOP_HDMI_APB_SEL
Definition: pll.c:121
TOP_SPIS_SEL
@ TOP_SPIS_SEL
Definition: pll.c:68
TOP_USB_3P_SEL
@ TOP_USB_3P_SEL
Definition: pll.c:90
TOP_DSP6_SEL
@ TOP_DSP6_SEL
Definition: pll.c:57
TOP_DSP5_SEL
@ TOP_DSP5_SEL
Definition: pll.c:56
TOP_ECC_SEL
@ TOP_ECC_SEL
Definition: pll.c:149
TOP_APLL3_SEL
@ TOP_APLL3_SEL
Definition: pll.c:134
TOP_I2SO2_M_SEL
@ TOP_I2SO2_M_SEL
Definition: pll.c:138
TOP_DGI_OUT_SEL
@ TOP_DGI_OUT_SEL
Definition: pll.c:125
TOP_SSUSB_XHCI_2P_SEL
@ TOP_SSUSB_XHCI_2P_SEL
Definition: pll.c:89
TOP_SPINFI_B_SEL
@ TOP_SPINFI_B_SEL
Definition: pll.c:147
TOP_DSP4_SEL
@ TOP_DSP4_SEL
Definition: pll.c:55
TOP_NNA0_SEL
@ TOP_NNA0_SEL
Definition: pll.c:126
TOP_INTDIR_SEL
@ TOP_INTDIR_SEL
Definition: pll.c:73
TOP_AUDIO_LOCAL_BUS_SEL
@ TOP_AUDIO_LOCAL_BUS_SEL
Definition: pll.c:150
TOP_A4SYS_SEL
@ TOP_A4SYS_SEL
Definition: pll.c:146
TOP_NFI1X_SEL
@ TOP_NFI1X_SEL
Definition: pll.c:148
TOP_HD20_DACR_REF_SEL
@ TOP_HD20_DACR_REF_SEL
Definition: pll.c:118
TOP_ASM_M_SEL
@ TOP_ASM_M_SEL
Definition: pll.c:130
TOP_AUD_IEC_SEL
@ TOP_AUD_IEC_SEL
Definition: pll.c:142
TOP_I2SO1_M_SEL
@ TOP_I2SO1_M_SEL
Definition: pll.c:137
TOP_TL_P1_SEL
@ TOP_TL_P1_SEL
Definition: pll.c:112
TOP_ASM_L_SEL
@ TOP_ASM_L_SEL
Definition: pll.c:131
TOP_HDMI_XTAL_SEL
@ TOP_HDMI_XTAL_SEL
Definition: pll.c:120
TOP_HD20_HDCP_C_SEL
@ TOP_HD20_HDCP_C_SEL
Definition: pll.c:119
TOP_USB_1P_SEL
@ TOP_USB_1P_SEL
Definition: pll.c:86
TOP_DISP_PWM1_SEL
@ TOP_DISP_PWM1_SEL
Definition: pll.c:83
TOP_I2SI1_M_SEL
@ TOP_I2SI1_M_SEL
Definition: pll.c:139
TOP_DISP_PWM0_SEL
@ TOP_DISP_PWM0_SEL
Definition: pll.c:82
TOP_VPP_SEL
@ TOP_VPP_SEL
Definition: pll.c:44
TOP_DPTX_M_SEL
@ TOP_DPTX_M_SEL
Definition: pll.c:141
TOP_WPE_VPP_SEL
@ TOP_WPE_VPP_SEL
Definition: pll.c:115
TOP_SPMI_M_MST_SEL
@ TOP_SPMI_M_MST_SEL
Definition: pll.c:109
mt_pll_set_tvd_pll1_freq
void mt_pll_set_tvd_pll1_freq(u32 freq)
Definition: pll.c:817
PLL_PCW_CHG
#define PLL_PCW_CHG
Definition: pll_common.h:19
NO_RSTB_SHIFT
#define NO_RSTB_SHIFT
Definition: pll_common.h:18
PLL_PWR_ON
#define PLL_PWR_ON
Definition: pll_common.h:14
mtk_topckgen
#define mtk_topckgen
Definition: pll_common.h:11
PLL
#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, _pcw_reg, _pcw_shift, _div_rate)
Definition: pll_common.h:44
PLL_ISO
#define PLL_ISO
Definition: pll_common.h:16
mtk_apmixed
#define mtk_apmixed
Definition: pll_common.h:12
fmeter_type
fmeter_type
Definition: pll_common.h:76
FMETER_CKGEN
@ FMETER_CKGEN
Definition: pll_common.h:78
FMETER_ABIST
@ FMETER_ABIST
Definition: pll_common.h:77
PERICFG_AO_BASE
@ PERICFG_AO_BASE
Definition: addressmap.h:61
SCP_ADSP_CFG_BASE
@ SCP_ADSP_CFG_BASE
Definition: addressmap.h:52
INFRACFG_AO_BCRM_BASE
@ INFRACFG_AO_BCRM_BASE
Definition: addressmap.h:29
u32
uint32_t u32
Definition: stdint.h:51
freq
Definition: dw_i2c.c:39
mt8186_mcucfg_regs::bus_plldiv_cfg
u32 bus_plldiv_cfg
Definition: mcucfg.h:200
mt8186_mcucfg_regs::cpu_plldiv_cfg1
u32 cpu_plldiv_cfg1
Definition: mcucfg.h:197
mt8186_mcucfg_regs::cpu_plldiv_cfg0
u32 cpu_plldiv_cfg0
Definition: mcucfg.h:196
mt8195_infracfg_ao_bcrm_regs
Definition: pll.c:16
mt8195_infracfg_ao_bcrm_regs::reserved1
u32 reserved1[13]
Definition: pll.c:17
mt8195_infracfg_ao_bcrm_regs::vdnr_dcm_top_infra_ctrl0
u32 vdnr_dcm_top_infra_ctrl0
Definition: pll.c:18
mt8195_infracfg_ao_regs::module_sw_cg_3_clr
u32 module_sw_cg_3_clr
Definition: infracfg.h:33
mt8195_infracfg_ao_regs::module_sw_cg_2_clr
u32 module_sw_cg_2_clr
Definition: infracfg.h:27
mt8195_infracfg_ao_regs::infra_bus_dcm_ctrl
u32 infra_bus_dcm_ctrl
Definition: infracfg.h:13
mt8195_infracfg_ao_regs::p2p_rx_clk_on
u32 p2p_rx_clk_on
Definition: infracfg.h:25
mt8195_infracfg_ao_regs::peri_bus_dcm_ctrl
u32 peri_bus_dcm_ctrl
Definition: infracfg.h:14
mt8195_infracfg_ao_regs::module_sw_cg_0_clr
u32 module_sw_cg_0_clr
Definition: infracfg.h:18
mt8195_infracfg_ao_regs::module_sw_cg_1_clr
u32 module_sw_cg_1_clr
Definition: infracfg.h:20
mt8195_infracfg_ao_regs::infra_aximem_idle_bit_en_0
u32 infra_aximem_idle_bit_en_0
Definition: infracfg.h:255
mt8195_pericfg_ao_regs
Definition: pll.c:24
mt8195_pericfg_ao_regs::reserved1
u32 reserved1[4]
Definition: pll.c:25
mt8195_pericfg_ao_regs::peri_module_sw_cg_0_set
u32 peri_module_sw_cg_0_set
Definition: pll.c:26
mt8195_scp_adsp_regs
Definition: pll.c:31
mt8195_scp_adsp_regs::audiodsp_ck_cg
u32 audiodsp_ck_cg
Definition: pll.c:33
mt8195_scp_adsp_regs::reserved1
u32 reserved1[96]
Definition: pll.c:32
mtk_spm_regs::ap_mdsrc_req
u32 ap_mdsrc_req
Definition: spm.h:314
mux_sel
Definition: pll.c:115
mux_sel::sel
u32 sel
Definition: pll.c:117
mux_sel::id
enum mux_id id
Definition: pll.c:116
mux
Definition: pll_common.h:22
pll
Definition: pll_common.h:32
pll::div_reg
void * div_reg
Definition: pll_common.h:35
rate
Definition: pll.c:262
rate::rate
u32 rate
Definition: pll.c:264
rate::id
enum pll_id id
Definition: pll.c:263
udelay
void udelay(uint32_t us)
Definition: udelay.c:15
count
#define count