6 #include <soc/addressmap.h>
7 #include <soc/infracfg.h>
54 #define MUX(_id, _reg, _mux_shift, _mux_width) \
56 .reg = &mtk_topckgen->_reg, \
57 .mux_shift = _mux_shift, \
58 .mux_width = _mux_width, \
217 static const struct pll plls[] = {
354 (1 << 10) | (1 << 9) | (1 << 5) | (1 << 4) | (1 << 2) |
355 (1 << 1) | (1 << 0));
357 (1 << 4) | (1 << 2) | (1 << 0));
392 if (
rate % 11025 == 0) {
398 mclk_div = (apll_clock / 256 /
rate) - 1;
399 assert(apll_clock ==
rate * 256 * (mclk_div + 1));
427 u32 mpll_sdm_pcw_20_0 = 0xF13B1;
static void write32(void *addr, uint32_t val)
#define assert(statement)
void mux_set_sel(const struct mux *mux, u32 sel)
int pll_set_rate(const struct pll *pll, u32 rate)
#define setbits32(addr, set)
#define clrsetbits32(addr, clear, set)
#define clrbits32(addr, clear)
static struct mt8173_infracfg_regs *const mt8173_infracfg
void mt_pll_post_init(void)
static const struct mux muxes[]
void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params)
static const struct rate rates[]
void mt_pll_raise_little_cpu_freq(u32 freq)
void mt_pll_enable_ssusb_clk(void)
#define MUX(_id, _reg, _mux_shift, _mux_width)
void mt_mem_pll_mux(void)
static const struct mux_sel mux_sels[]
const u32 mmpll_div_rate[]
void pll_set_pcw_change(const struct pll *pll)
static const struct pll plls[]
const u32 univpll_div_rate[]
void mt_pll_set_aud_div(u32 rate)
void mt_mem_pll_config_post(void)
#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, _pcw_reg, _pcw_shift, _div_rate)
Defines the SDRAM parameter structure.