coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef __ARCH_ROMSTAGE_H__
4 #define __ARCH_ROMSTAGE_H__
5 
6 #include <stddef.h>
7 #include <stdint.h>
8 #include <cpu/x86/mtrr.h>
9 
10 void mainboard_romstage_entry(void);
11 
12 /*
13  * Support setting up a stack frame consisting of MTRR information
14  * for use in bootstrapping the caching attributes after cache-as-ram
15  * is torn down.
16  */
17 
18 struct postcar_frame {
21  struct var_mtrr_context ctx;
22 };
23 
24 /*
25  * Initialize postcar_frame object allocating stack from cbmem,
26  * with stack_size == 0, default 4 KiB is allocated.
27  * Returns 0 on success, < 0 on error.
28  */
29 int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);
30 
31 /*
32  * Add variable MTRR covering the provided range with MTRR type.
33  */
34 void postcar_frame_add_mtrr(struct postcar_frame *pcf,
35  uintptr_t addr, size_t size, int type);
36 
37 /*
38  * Add variable MTRR covering the memory-mapped ROM with given MTRR type.
39  */
40 void postcar_frame_add_romcache(struct postcar_frame *pcf, int type);
41 
42 /*
43  * fill_postcar_frame() is called after raminit completes and right before
44  * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()
45  * to tag memory ranges as cacheable to speed up execution of postcar and
46  * early ramstage.
47  */
48 void fill_postcar_frame(struct postcar_frame *pcf);
49 
50 /*
51  * prepare_and_run_postcar() determines the stack to use after
52  * cache-as-ram is torn down as well as the MTRR settings to use.
53  */
54 void prepare_and_run_postcar(struct postcar_frame *pcf);
55 
56 /*
57  * Load and run a program that takes control of execution that
58  * tears down CAR and loads ramstage. The postcar_frame object
59  * indicates how to set up the frame. If caching is enabled at
60  * the time of the call it is up to the platform code to handle
61  * coherency with dirty lines in the cache using some mechanism
62  * such as platform_prog_run() because run_postcar_phase()
63  * utilizes prog_run() internally.
64  */
65 void run_postcar_phase(struct postcar_frame *pcf);
66 
67 /*
68  * Systems without a native coreboot cache-as-ram teardown may implement
69  * this to use an alternate method.
70  */
71 void late_car_teardown(void);
72 
73 /*
74  * Cache the TSEG region at the top of ram. This region is
75  * not restricted to SMM mode until SMM has been relocated.
76  * By setting the region to cacheable it provides faster access
77  * when relocating the SMM handler as well as using the TSEG
78  * region for other purposes.
79  */
81 
82 #endif /* __ARCH_ROMSTAGE_H__ */
void prepare_and_run_postcar(struct postcar_frame *pcf)
void late_car_teardown(void)
Definition: postcar.c:15
void run_postcar_phase(struct postcar_frame *pcf)
int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type)
void mainboard_romstage_entry(void)
Definition: car.c:26
void fill_postcar_frame(struct postcar_frame *pcf)
Definition: car.c:13
void postcar_enable_tseg_cache(struct postcar_frame *pcf)
void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
static u32 addr
Definition: cirrus.c:14
unsigned int type
Definition: edid.c:57
unsigned long uintptr_t
Definition: stdint.h:21
int skip_common_mtrr
Definition: romstage.h:20
uintptr_t stack
Definition: romstage.h:19
struct var_mtrr_context ctx
Definition: romstage.h:21