coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ARCH_ROMSTAGE_H__
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#define __ARCH_ROMSTAGE_H__
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#include <
stddef.h
>
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#include <
stdint.h
>
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#include <
cpu/x86/mtrr.h
>
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void
mainboard_romstage_entry
(
void
);
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/*
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* Support setting up a stack frame consisting of MTRR information
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* for use in bootstrapping the caching attributes after cache-as-ram
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* is torn down.
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*/
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struct
postcar_frame
{
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uintptr_t
stack
;
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int
skip_common_mtrr
;
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struct
var_mtrr_context
ctx
;
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};
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/*
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* Initialize postcar_frame object allocating stack from cbmem,
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* with stack_size == 0, default 4 KiB is allocated.
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* Returns 0 on success, < 0 on error.
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*/
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int
postcar_frame_init
(
struct
postcar_frame
*pcf,
size_t
stack_size);
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/*
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* Add variable MTRR covering the provided range with MTRR type.
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*/
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void
postcar_frame_add_mtrr
(
struct
postcar_frame
*pcf,
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uintptr_t
addr
,
size_t
size,
int
type
);
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/*
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* Add variable MTRR covering the memory-mapped ROM with given MTRR type.
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*/
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void
postcar_frame_add_romcache
(
struct
postcar_frame
*pcf,
int
type
);
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/*
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* fill_postcar_frame() is called after raminit completes and right before
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* calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()
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* to tag memory ranges as cacheable to speed up execution of postcar and
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* early ramstage.
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*/
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void
fill_postcar_frame
(
struct
postcar_frame
*pcf);
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/*
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* prepare_and_run_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use.
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*/
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void
prepare_and_run_postcar
(
struct
postcar_frame
*pcf);
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/*
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* Load and run a program that takes control of execution that
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* tears down CAR and loads ramstage. The postcar_frame object
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* indicates how to set up the frame. If caching is enabled at
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* the time of the call it is up to the platform code to handle
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* coherency with dirty lines in the cache using some mechanism
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* such as platform_prog_run() because run_postcar_phase()
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* utilizes prog_run() internally.
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*/
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void
run_postcar_phase
(
struct
postcar_frame
*pcf);
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/*
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* Systems without a native coreboot cache-as-ram teardown may implement
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* this to use an alternate method.
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*/
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void
late_car_teardown
(
void
);
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/*
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* Cache the TSEG region at the top of ram. This region is
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* not restricted to SMM mode until SMM has been relocated.
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* By setting the region to cacheable it provides faster access
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* when relocating the SMM handler as well as using the TSEG
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* region for other purposes.
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*/
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void
postcar_enable_tseg_cache
(
struct
postcar_frame
*pcf);
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#endif
/* __ARCH_ROMSTAGE_H__ */
prepare_and_run_postcar
void prepare_and_run_postcar(struct postcar_frame *pcf)
Definition:
postcar_loader.c:95
late_car_teardown
void late_car_teardown(void)
Definition:
postcar.c:15
run_postcar_phase
void run_postcar_phase(struct postcar_frame *pcf)
Definition:
postcar_loader.c:175
postcar_frame_init
int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
Definition:
postcar_loader.c:30
postcar_frame_add_mtrr
void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type)
Definition:
postcar_loader.c:71
mainboard_romstage_entry
void mainboard_romstage_entry(void)
Definition:
car.c:26
fill_postcar_frame
void fill_postcar_frame(struct postcar_frame *pcf)
Definition:
car.c:13
postcar_enable_tseg_cache
void postcar_enable_tseg_cache(struct postcar_frame *pcf)
Definition:
postcar_loader.c:159
postcar_frame_add_romcache
void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
Definition:
postcar_loader.c:77
addr
static u32 addr
Definition:
cirrus.c:14
type
unsigned int type
Definition:
edid.c:57
stddef.h
stdint.h
uintptr_t
unsigned long uintptr_t
Definition:
stdint.h:21
postcar_frame
Definition:
romstage.h:18
postcar_frame::skip_common_mtrr
int skip_common_mtrr
Definition:
romstage.h:20
postcar_frame::stack
uintptr_t stack
Definition:
romstage.h:19
postcar_frame::ctx
struct var_mtrr_context ctx
Definition:
romstage.h:21
var_mtrr_context
Definition:
mtrr.h:121
mtrr.h
src
arch
x86
include
arch
romstage.h
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