coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
car.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
arch/romstage.h
>
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#include <
arch/symbols.h
>
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#include <
cbfs.h
>
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#include <
cbmem.h
>
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#include <
console/console.h
>
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#include <
commonlib/helpers.h
>
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#include <
cpu/x86/mtrr.h
>
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#include <
fsp/car.h
>
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#include <fsp/util.h>
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void
fill_postcar_frame
(
struct
postcar_frame
*pcf)
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{
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uintptr_t
top_of_ram;
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations. */
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top_of_ram =
ALIGN_DOWN
((
uintptr_t
)
cbmem_top
(), 8*
MiB
);
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postcar_frame_add_mtrr
(pcf, top_of_ram - 8*
MiB
, 16*
MiB
,
MTRR_TYPE_WRBACK
);
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}
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/* This is the romstage entry called from cpu/intel/car/romstage.c */
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void
mainboard_romstage_entry
(
void
)
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{
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/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
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* is still enabled. We can directly access work buffer here. */
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void
*fsp =
cbfs_map
(
"fsp.bin"
,
NULL
);
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if
(!fsp)
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die_with_post_code
(
POST_INVALID_CBFS
,
"Unable to locate fsp.bin"
);
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/* This leaks a mapping which this code assumes is benign as
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* the flash is memory mapped CPU's address space. */
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FSP_INFO_HEADER *fih =
find_fsp
((
uintptr_t
)fsp);
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if
(!fih)
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die
(
"Invalid FSP header\n"
);
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cache_as_ram_stage_main
(fih);
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}
romstage.h
postcar_frame_add_mtrr
void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type)
Definition:
postcar_loader.c:71
symbols.h
ALIGN_DOWN
#define ALIGN_DOWN(x, a)
Definition:
helpers.h:18
MiB
#define MiB
Definition:
helpers.h:76
cbfs.h
cbfs_map
static void * cbfs_map(const char *name, size_t *size_out)
Definition:
cbfs.h:246
cbmem.h
cbmem_top
void * cbmem_top(void)
Definition:
imd_cbmem.c:18
die
void __noreturn die(const char *fmt,...)
Definition:
die.c:17
console.h
die_with_post_code
#define die_with_post_code(value, fmt,...)
Definition:
console.h:21
mainboard_romstage_entry
void mainboard_romstage_entry(void)
Definition:
car.c:26
fill_postcar_frame
void fill_postcar_frame(struct postcar_frame *pcf)
Definition:
car.c:13
car.h
cache_as_ram_stage_main
void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
Definition:
romstage.c:95
find_fsp
FSP_INFO_HEADER * find_fsp(uintptr_t fsp_base_address)
Definition:
fsp_util.c:12
helpers.h
POST_INVALID_CBFS
#define POST_INVALID_CBFS
Invalid or corrupt CBFS.
Definition:
post_codes.h:330
NULL
#define NULL
Definition:
stddef.h:19
uintptr_t
unsigned long uintptr_t
Definition:
stdint.h:21
postcar_frame
Definition:
romstage.h:18
mtrr.h
MTRR_TYPE_WRBACK
#define MTRR_TYPE_WRBACK
Definition:
mtrr.h:14
src
drivers
intel
fsp1_1
car.c
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