coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3
#include <
bootblock_common.h
>
4
#include <
device/pnp_ops.h
>
5
#include <
device/dram/ddr3.h
>
6
#include <
northbridge/intel/sandybridge/raminit_native.h
>
7
#include <
southbridge/intel/bd82x6x/pch.h
>
8
#include <
superio/nuvoton/common/nuvoton.h
>
9
#include <
superio/nuvoton/nct6776/nct6776.h
>
10
11
const
struct
southbridge_usb_port
mainboard_usb_ports
[] = {
12
{ 1, 0, 0 },
13
{ 1, 0, 0 },
14
{ 1, 0, 1 },
15
{ 1, 0, 1 },
16
{ 1, 0, 2 },
17
{ 1, 0, 2 },
18
{ 1, 0, 3 },
19
{ 1, 0, 3 },
20
{ 1, 0, 4 },
21
{ 1, 0, 4 },
22
{ 1, 0, 5 },
23
{ 1, 0, 5 },
24
{ 1, 0, 6 },
25
{ 1, 0, 6 },
26
};
27
28
void
bootblock_mainboard_early_init
(
void
)
29
{
30
static
const
pnp_devfn_t
GLOBAL_PSEUDO_DEV =
PNP_DEV
(0x2e, 0);
31
static
const
pnp_devfn_t
ACPI_DEV
=
PNP_DEV
(0x2e,
NCT6776_ACPI
);
32
33
nuvoton_pnp_enter_conf_state
(GLOBAL_PSEUDO_DEV);
34
35
/* Select HWM/LED functions instead of floppy functions. */
36
pnp_write_config
(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
37
pnp_write_config
(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
38
39
/* Power RAM in S3. */
40
pnp_set_logical_device
(
ACPI_DEV
);
41
pnp_write_config
(
ACPI_DEV
, 0xe4, 0x10);
42
43
nuvoton_pnp_exit_conf_state
(GLOBAL_PSEUDO_DEV);
44
}
45
46
void
mainboard_get_spd
(
spd_raw_data
*spd,
bool
id_only)
47
{
48
read_spd
(&spd[0], 0x50, id_only);
49
read_spd
(&spd[1], 0x51, id_only);
50
read_spd
(&spd[2], 0x52, id_only);
51
read_spd
(&spd[3], 0x53, id_only);
52
}
bootblock_common.h
ddr3.h
Utilities for decoding DDR3 SPDs.
spd_raw_data
u8 spd_raw_data[256]
Definition:
ddr3.h:156
bootblock_mainboard_early_init
void bootblock_mainboard_early_init(void)
Definition:
early_init.c:11
mainboard_get_spd
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition:
early_init.c:25
mainboard_usb_ports
const struct southbridge_usb_port mainboard_usb_ports[]
Definition:
early_init.c:8
ACPI_DEV
#define ACPI_DEV
Definition:
early_init.c:12
nct6776.h
NCT6776_ACPI
#define NCT6776_ACPI
Definition:
nct6776.h:18
read_spd
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition:
raminit.c:138
nuvoton_pnp_enter_conf_state
void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
Definition:
early_serial.c:33
nuvoton_pnp_exit_conf_state
void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
Definition:
early_serial.c:41
nuvoton.h
pnp_set_logical_device
void pnp_set_logical_device(struct device *dev)
Definition:
pnp_device.c:59
pnp_write_config
void pnp_write_config(struct device *dev, u8 reg, u8 value)
Definition:
pnp_device.c:38
pnp_ops.h
PNP_DEV
#define PNP_DEV(PORT, FUNC)
Definition:
pnp_type.h:10
pnp_devfn_t
u32 pnp_devfn_t
Definition:
pnp_type.h:8
raminit_native.h
pch.h
southbridge_usb_port
Definition:
pch.h:56
src
mainboard
asus
maximus_iv_gene-z
early_init.c
Generated by
1.9.1