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#define | CROS_GPIO_DEVICE_NAME "BayTrail" |
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#define | GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) |
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#define | GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) |
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#define | GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) |
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#define | PAD_BASE_DIRQ_OFFSET 0x980 |
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#define | PAD_CONF0_REG 0x0 |
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#define | PAD_CONF1_REG 0x4 |
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#define | PAD_VAL_REG 0x8 |
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#define | GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) |
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#define | GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) |
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#define | GP_LEGACY_BASE_NONE 0xFFFF |
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#define | LEGACY_USE_SEL_REG 0x00 |
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#define | LEGACY_IO_SEL_REG 0x04 |
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#define | LEGACY_GP_LVL_REG 0x08 |
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#define | LEGACY_TPE_REG 0x0C |
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#define | LEGACY_TNE_REG 0x10 |
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#define | LEGACY_TS_REG 0x14 |
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#define | LEGACY_WAKE_EN_REG 0x18 |
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#define | GPNCORE_COUNT 27 |
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#define | GPSCORE_COUNT 102 |
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#define | GPSSUS_COUNT 44 |
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#define | GPIO_USE_MMIO 0 |
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#define | GPIO_USE_LEGACY 1 |
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#define | GPIO_DIR_OUTPUT 0 |
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#define | GPIO_DIR_INPUT 1 |
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#define | GPIO_LEVEL_LOW 0 |
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#define | GPIO_LEVEL_HIGH 1 |
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#define | GPIO_PEDGE_DISABLE 0 |
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#define | GPIO_PEDGE_ENABLE 1 |
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#define | GPIO_NEDGE_DISABLE 0 |
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#define | GPIO_NEDGE_ENABLE 1 |
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#define | PAD_MASK2_DISABLE (1 << 29) |
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#define | PAD_IRQ_EN (1 << 27) |
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#define | PAD_TNE_IRQ (1 << 26) |
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#define | PAD_TPE_IRQ (1 << 25) |
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#define | PAD_LEVEL_IRQ (1 << 24) |
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#define | PAD_EDGE_IRQ (0 << 24) |
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#define | PAD_SLOWGF_ENABLE (1 << 17) |
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#define | PAD_FASTGF_ENABLE (1 << 16) |
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#define | PAD_HYST_DISABLE (1 << 15) |
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#define | PAD_HYST_ENABLE (0 << 15) |
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#define | PAD_HYST_CTRL_DEFAULT (2 << 13) |
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#define | PAD_FLOP_BYPASS (1 << 11) |
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#define | PAD_FLOP_ENABLE (0 << 11) |
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#define | PAD_PU_2K (0 << 9) |
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#define | PAD_PU_10K (1 << 9) |
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#define | PAD_PU_20K (2 << 9) |
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#define | PAD_PU_40K (3 << 9) |
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#define | PAD_PULL_DISABLE (0 << 7) |
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#define | PAD_PULL_UP (1 << 7) |
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#define | PAD_PULL_DOWN (2 << 7) |
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#define | PAD_FUNC0 0x0 |
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#define | PAD_FUNC1 0x1 |
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#define | PAD_FUNC2 0x2 |
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#define | PAD_FUNC3 0x3 |
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#define | PAD_FUNC4 0x4 |
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#define | PAD_FUNC5 0x5 |
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#define | PAD_FUNC6 0x6 |
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#define | PAD_CONFIG0_DEFAULT |
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#define | PAD_CONFIG1_DEFAULT 0x8000 |
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#define | PAD_VAL_INPUT_DISABLE (1 << 2) |
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#define | PAD_VAL_INPUT_ENABLE (0 << 2) |
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#define | PAD_VAL_OUTPUT_DISABLE (1 << 1) |
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#define | PAD_VAL_OUTPUT_ENABLE (0 << 1) |
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#define | PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) |
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#define | PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) |
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#define | PAD_VAL_HIGH (1 << 0) |
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#define | PAD_VAL_LOW (0 << 0) |
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#define | PAD_VAL_DEFAULT PAD_VAL_INPUT |
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#define | GPIO_INPUT_PU_10K |
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#define | GPIO_INPUT_PU_20K |
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#define | GPIO_INPUT_PD_10K |
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#define | GPIO_INPUT_PD_20K |
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#define | GPIO_INPUT_NOPU |
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#define | GPIO_INPUT_LEGACY_NOPU |
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#define | GPIO_DIRQ |
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#define | GPIO_DIRQ_LEVELHIGH_NO_PULL |
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#define | GPIO_DIRQ_LEVELLOW_PU_20K |
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#define | GPIO_DIRQ_EDGELOW_PU_20K |
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#define | GPIO_DIRQ_EDGEHIGH_PD_20K |
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#define | GPIO_DIRQ_EDGELOW_PD_20K |
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#define | GPIO_DIRQ_EDGEBOTH_PU_20K |
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#define | GPIO_OUT_LOW |
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#define | GPIO_OUT_HIGH |
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#define | GPIO_FUNC(_func, _pudir, _str) |
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#define | GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) |
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#define | GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) |
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#define | GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) |
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#define | GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) |
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#define | GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) |
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#define | GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) |
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#define | GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) |
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#define | GPIO_ACPI_SCI |
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#define | GPIO_ACPI_WAKE |
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#define | GPIO_ACPI_SMI |
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#define | GPIO_LIST_END 0xffffffff |
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#define | GPIO_END { .pad_conf0 = GPIO_LIST_END } |
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#define | GPIO_INPUT GPIO_INPUT_NOPU |
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#define | GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU |
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#define | GPIO_INPUT_PU GPIO_INPUT_PU_20K |
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#define | GPIO_INPUT_PD GPIO_INPUT_PD_20K |
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#define | GPIO_NC GPIO_OUT_HIGH |
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#define | GPIO_DEFAULT GPIO_FUNC0 |
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#define | GPIO_MAX_DIRQS 16 |
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#define | GPIO_NONE 255 |
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#define | GPNCORE_GPIO_F1_RANGE_START GPIO_NONE |
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#define | GPNCORE_GPIO_F1_RANGE_END GPIO_NONE |
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#define | GPSCORE_GPIO_F1_RANGE_START 92 |
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#define | GPSCORE_GPIO_F1_RANGE_END 93 |
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#define | GPSSUS_GPIO_F1_RANGE_START 11 |
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#define | GPSSUS_GPIO_F1_RANGE_END 21 |
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#define | UART_RXD_PAD 82 |
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#define | UART_TXD_PAD 83 |
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#define | PCU_SMB_CLK_PAD 88 |
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#define | PCU_SMB_DATA_PAD 90 |
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#define | SOC_DDI1_VDDEN_PAD 16 |
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