coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
struct | lp0_header |
Enumerations | |
enum | { UP_TAG_BASE = 0x60000000 , TIMER_BASE = 0x60005000 , CLK_RST_BASE = 0x60006000 , FLOW_CTLR_BASE = 0x60007000 , TEGRA_EVP_BASE = 0x6000f000 , PMC_CTLR_BASE = 0x7000e400 , MC_CTLR_BASE = 0x70019000 , SYSCTR_CTLR_BASE = 0x700f0000 } |
enum | { UP_TAG_AVP = 0xaaaaaaaa } |
enum | { SWR_TRIG_SYS_RST = 0x1 << 2 } |
enum | { CCLK_PLLP_BURST_POLICY = 0x20004444 } |
enum | { SUPER_CDIV_ENB = 0x1 << 31 } |
enum | { OSC_XOE = 0x1 << 0 , OSC_XOFS_SHIFT = 4 , OSC_XOFS_MASK = 0x3f << OSC_XOFS_SHIFT , OSC_FREQ_SHIFT = 28 , OSC_FREQ_MASK = 0xf << OSC_FREQ_SHIFT } |
enum | { OSC_FREQ_13 = 0 , OSC_FREQ_16P8 = 1 , OSC_FREQ_19P2 = 4 , OSC_FREQ_38P4 = 5 , OSC_FREQ_12 = 8 , OSC_FREQ_48 = 9 , OSC_FREQ_26 = 12 } |
enum | { PLLU_DIVM_SHIFT = 0 , PLLU_DIVN_SHIFT = 8 , PLLU_OVERRIDE = 0x1 << 24 , PLLU_ENABLE = 0x1 << 30 , PLLU_BYPASS = 0x1 << 31 } |
enum | { PLLU_LFCON_SHIFT = 4 , PLLU_CPCON_SHIFT = 8 , PLLU_LOCK_ENABLE = 22 } |
enum | { PLLX_ENABLE = 0x1 << 30 } |
enum | { SWR_CSITE_RST = 0x1 << 9 } |
enum | { CLK_ENB_CPU = 0x1 << 0 } |
enum | { CLK_ENB_CSITE = 0x1 << 9 } |
enum | { CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0 , CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT } |
enum | { MSELECT_CLK_DIV_SHIFT = 0 , MSELECT_CLK_SRC_SHIFT = 29 , MSELECT_CLK_SRC_PLLP_OUT0 = 0x0 << MSELECT_CLK_SRC_SHIFT , MSELECT_CLK_SRC_PLLC2_OUT0 = 0x1 << MSELECT_CLK_SRC_SHIFT , MSELECT_CLK_SRC_PLLC_OUT0 = 0x2 << MSELECT_CLK_SRC_SHIFT , MSELECT_CLK_SRC_PLLC3_OUT0 = 0x3 << MSELECT_CLK_SRC_SHIFT } |
enum | { SWR_MSELECT_RST = 0x1 << 3 } |
enum | { CLK_ENB_CPUG = 0x1 << 0 , CLK_ENB_CPULP = 0x1 << 1 , CLK_ENB_MSELECT = 0x1 << 3 } |
enum | { CLR_CPURESET0 = 0x1 << 0 , CLR_CPURESET1 = 0x1 << 1 , CLR_CPURESET2 = 0x1 << 2 , CLR_CPURESET3 = 0x1 << 3 , CLR_DBGRESET0 = 0x1 << 12 , CLR_DBGRESET1 = 0x1 << 13 , CLR_DBGRESET2 = 0x1 << 14 , CLR_DBGRESET3 = 0x1 << 15 , CLR_CORERESET0 = 0x1 << 16 , CLR_CORERESET1 = 0x1 << 17 , CLR_CORERESET2 = 0x1 << 18 , CLR_CORERESET3 = 0x1 << 19 , CLR_CXRESET0 = 0x1 << 20 , CLR_CXRESET1 = 0x1 << 21 , CLR_CXRESET2 = 0x1 << 22 , CLR_CXRESET3 = 0x1 << 23 , CLR_NONCPURESET = 0x1 << 29 } |
enum | { EVENT_MSEC = 0x1 << 24 , EVENT_JTAG = 0x1 << 28 , FLOW_MODE_SHIFT = 29 , FLOW_MODE_STOP = 2 << FLOW_MODE_SHIFT } |
enum | { FLOW_CLUSTER_ACTIVE_LP = 0x1 << 0 } |
enum | { RAM_REPAIR_REQ = 0x1 << 0 , RAM_REPAIR_STS = 0x1 << 1 } |
enum | { PARTID_CRAIL = 0 , PARTID_CELP = 12 , PARTID_CE0 = 14 , PARTID_C0NC = 15 , PARTID_C1NC = 16 } |
enum | { PWRGATE_TOGGLE_START = 0x1 << 8 } |
enum | { PMC_SCRATCH4_LP = 0x1 << 31 } |
enum | { PMC_XOFS_SHIFT = 1 , PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT } |
enum | { VIDEO_PROTECT_WRITE_ACCESS_DISABLE = 0x1 << 0 , VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1 } |
enum | { TSC_CNTCR_ENABLE = 0x1 << 0 , TSC_CNTCR_HDBG = 0x1 << 1 } |
Functions | |
static __always_inline void __noreturn | halt (void) |
static uint32_t | read32 (const void *addr) |
static void | write32 (void *addr, uint32_t val) |
static void | setbits32 (uint32_t bits, void *addr) |
static void | clrbits32 (uint32_t bits, void *addr) |
static void __noreturn | reset (void) |
static void | udelay (unsigned int usecs) |
static int | wakeup_on_lp (void) |
static uint32_t | get_wakeup_vector (void) |
static unsigned int | get_osc_freq (void) |
static void | config_oscillator (void) |
static void | config_pllu (void) |
static void | config_tsc (void) |
static void | enable_cpu_clocks (void) |
static void | config_core_sight (void) |
static void | config_mselect (void) |
static void | clear_cpu_resets (void) |
void | ram_repair (void) |
static void | power_on_partition (unsigned int id) |
static void | power_on_main_cpu (void) |
void | lp0_resume (void) |
anonymous enum |
Enumerator | |
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UP_TAG_BASE | |
TIMER_BASE | |
CLK_RST_BASE | |
FLOW_CTLR_BASE | |
TEGRA_EVP_BASE | |
PMC_CTLR_BASE | |
MC_CTLR_BASE | |
SYSCTR_CTLR_BASE |
Definition at line 4 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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UP_TAG_AVP |
Definition at line 17 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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SWR_TRIG_SYS_RST |
Definition at line 26 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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CCLK_PLLP_BURST_POLICY |
Definition at line 31 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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SUPER_CDIV_ENB |
Definition at line 36 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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OSC_XOE | |
OSC_XOFS_SHIFT | |
OSC_XOFS_MASK | |
OSC_FREQ_SHIFT | |
OSC_FREQ_MASK |
Definition at line 41 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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OSC_FREQ_13 | |
OSC_FREQ_16P8 | |
OSC_FREQ_19P2 | |
OSC_FREQ_38P4 | |
OSC_FREQ_12 | |
OSC_FREQ_48 | |
OSC_FREQ_26 |
Definition at line 48 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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PLLU_DIVM_SHIFT | |
PLLU_DIVN_SHIFT | |
PLLU_OVERRIDE | |
PLLU_ENABLE | |
PLLU_BYPASS |
Definition at line 59 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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PLLU_LFCON_SHIFT | |
PLLU_CPCON_SHIFT | |
PLLU_LOCK_ENABLE |
Definition at line 68 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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PLLX_ENABLE |
Definition at line 75 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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SWR_CSITE_RST |
Definition at line 80 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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CLK_ENB_CPU |
Definition at line 85 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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CLK_ENB_CSITE |
Definition at line 91 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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CAR2PMC_CPU_ACK_WIDTH_SHIFT | |
CAR2PMC_CPU_ACK_WIDTH_MASK |
Definition at line 97 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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MSELECT_CLK_DIV_SHIFT | |
MSELECT_CLK_SRC_SHIFT | |
MSELECT_CLK_SRC_PLLP_OUT0 | |
MSELECT_CLK_SRC_PLLC2_OUT0 | |
MSELECT_CLK_SRC_PLLC_OUT0 | |
MSELECT_CLK_SRC_PLLC3_OUT0 |
Definition at line 104 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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SWR_MSELECT_RST |
Definition at line 114 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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CLK_ENB_CPUG | |
CLK_ENB_CPULP | |
CLK_ENB_MSELECT |
Definition at line 119 of file tegra_lp0_resume.c.
anonymous enum |
Definition at line 129 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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EVENT_MSEC | |
EVENT_JTAG | |
FLOW_MODE_SHIFT | |
FLOW_MODE_STOP |
Definition at line 155 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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FLOW_CLUSTER_ACTIVE_LP |
Definition at line 164 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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RAM_REPAIR_REQ | |
RAM_REPAIR_STS |
Definition at line 172 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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PARTID_CRAIL | |
PARTID_CELP | |
PARTID_CE0 | |
PARTID_C0NC | |
PARTID_C1NC |
Definition at line 178 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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PWRGATE_TOGGLE_START |
Definition at line 189 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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PMC_SCRATCH4_LP |
Definition at line 196 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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PMC_XOFS_SHIFT | |
PMC_XOFS_MASK |
Definition at line 206 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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VIDEO_PROTECT_WRITE_ACCESS_DISABLE | |
VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS |
Definition at line 216 of file tegra_lp0_resume.c.
anonymous enum |
Enumerator | |
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TSC_CNTCR_ENABLE | |
TSC_CNTCR_HDBG |
Definition at line 223 of file tegra_lp0_resume.c.
Definition at line 425 of file tegra_lp0_resume.c.
References clk_rst_rst_cpug_cmplx_clr_ptr, clk_rst_rst_cpulp_cmplx_clr_ptr, CLR_CORERESET0, CLR_CORERESET1, CLR_CORERESET2, CLR_CORERESET3, CLR_CPURESET0, CLR_CPURESET1, CLR_CPURESET2, CLR_CPURESET3, CLR_CXRESET0, CLR_CXRESET1, CLR_CXRESET2, CLR_CXRESET3, CLR_DBGRESET0, CLR_DBGRESET1, CLR_DBGRESET2, CLR_DBGRESET3, CLR_NONCPURESET, and write32().
Referenced by lp0_resume().
Definition at line 251 of file tegra_lp0_resume.c.
References addr, read32(), and write32().
Referenced by lp0_resume().
Definition at line 395 of file tegra_lp0_resume.c.
References CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr, clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST, and write32().
Referenced by lp0_resume().
Definition at line 409 of file tegra_lp0_resume.c.
References CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr, clk_rst_clk_src_mselect_ptr, clk_rst_rst_dev_v_clr_ptr, MSELECT_CLK_DIV_SHIFT, MSELECT_CLK_SRC_PLLP_OUT0, SWR_MSELECT_RST, udelay(), and write32().
Referenced by lp0_resume().
Definition at line 286 of file tegra_lp0_resume.c.
References clk_rst_osc_ctrl_ptr, OSC_XOE, OSC_XOFS_MASK, OSC_XOFS_SHIFT, pmc_ctlr_osc_edpd_over_ptr, PMC_XOFS_MASK, PMC_XOFS_SHIFT, read32(), and write32().
Referenced by lp0_resume().
Definition at line 300 of file tegra_lp0_resume.c.
References base, clk_rst_pllu_base_ptr, clk_rst_pllu_misc_ptr, get_osc_freq(), misc, OSC_FREQ_12, OSC_FREQ_16P8, OSC_FREQ_19P2, OSC_FREQ_26, OSC_FREQ_38P4, OSC_FREQ_48, PLLU_BYPASS, PLLU_CPCON_SHIFT, PLLU_DIVM_SHIFT, PLLU_DIVN_SHIFT, PLLU_ENABLE, PLLU_LFCON_SHIFT, PLLU_LOCK_ENABLE, PLLU_OVERRIDE, and write32().
Referenced by lp0_resume().
Definition at line 355 of file tegra_lp0_resume.c.
References get_osc_freq(), OSC_FREQ_12, OSC_FREQ_16P8, OSC_FREQ_19P2, OSC_FREQ_26, OSC_FREQ_38P4, OSC_FREQ_48, setbits32(), sysctr_cntcr_ptr, sysctr_cntfid0_ptr, TSC_CNTCR_ENABLE, TSC_CNTCR_HDBG, and write32().
Referenced by lp0_resume().
Definition at line 387 of file tegra_lp0_resume.c.
References CLK_ENB_CPU, CLK_ENB_CPUG, CLK_ENB_CPULP, clk_rst_clk_enb_l_set_ptr, clk_rst_clk_enb_v_set_ptr, and write32().
Referenced by lp0_resume().
Definition at line 280 of file tegra_lp0_resume.c.
References clk_rst_osc_ctrl_ptr, OSC_FREQ_MASK, OSC_FREQ_SHIFT, and read32().
Referenced by config_pllu(), and config_tsc().
Definition at line 275 of file tegra_lp0_resume.c.
References pmc_ctlr_scratch41_ptr, and read32().
Referenced by lp0_resume().
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Definition at line 231 of file tegra_lp0_resume.c.
Referenced by reset().
Definition at line 512 of file tegra_lp0_resume.c.
References CAR2PMC_CPU_ACK_WIDTH_MASK, CAR2PMC_CPU_ACK_WIDTH_SHIFT, CCLK_PLLP_BURST_POLICY, clear_cpu_resets(), clk_rst_cclk_burst_policy_ptr, clk_rst_cpu_softrst_ctrl2_ptr, clk_rst_pllx_base_ptr, clk_rst_super_cclk_div_ptr, clrbits32(), config_core_sight(), config_mselect(), config_oscillator(), config_pllu(), config_tsc(), enable_cpu_clocks(), EVENT_JTAG, evp_cpu_reset_ptr, FLOW_CLUSTER_ACTIVE_LP, flow_ctlr_cluster_control_ptr, flow_ctlr_halt_cop_events_ptr, FLOW_MODE_STOP, get_wakeup_vector(), mc_video_protect_reg_ctrl_ptr, mc_video_protect_size_mb_ptr, PLLX_ENABLE, power_on_main_cpu(), ram_repair(), read32(), reset(), setbits32(), SUPER_CDIV_ENB, UP_TAG_AVP, up_tag_ptr, VIDEO_PROTECT_WRITE_ACCESS_DISABLE, wakeup_on_lp(), and write32().
Definition at line 477 of file tegra_lp0_resume.c.
References PARTID_C0NC, PARTID_C1NC, PARTID_CE0, PARTID_CELP, PARTID_CRAIL, pmc_ctlr_cpupwrgood_timer_ptr, power_on_partition(), read32(), wakeup_on_lp(), and write32().
Referenced by lp0_resume().
Definition at line 460 of file tegra_lp0_resume.c.
References pmc_ctlr_clamp_status_ptr, pmc_ctlr_pwrgate_status_ptr, pmc_ctlr_pwrgate_toggle_ptr, PWRGATE_TOGGLE_START, read32(), and write32().
Referenced by power_on_main_cpu().
Definition at line 444 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
Definition at line 236 of file tegra_lp0_resume.c.
References addr.
Referenced by clrbits32(), config_oscillator(), get_osc_freq(), get_wakeup_vector(), lp0_resume(), power_on_main_cpu(), power_on_partition(), ram_repair(), setbits32(), udelay(), and wakeup_on_lp().
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Definition at line 256 of file tegra_lp0_resume.c.
References clk_rst_rst_devices_l_ptr, halt(), SWR_TRIG_SYS_RST, and write32().
Referenced by agesa_execute_state(), clock_reset_bcr(), ddr3_mem_ctrl_init(), intel_early_me_init_done(), ledc_transfer(), lp0_resume(), mtk_dpintf_sw_reset(), sdram_checkreset(), setup_pch_lp_gpios(), and start_cpu().
Definition at line 246 of file tegra_lp0_resume.c.
References addr, read32(), and write32().
Referenced by config_tsc(), lp0_resume(), and ram_repair().
Definition at line 262 of file tegra_lp0_resume.c.
References read32(), and timer_us_ptr.
Referenced by config_mselect().
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Definition at line 270 of file tegra_lp0_resume.c.
References pmc_ctlr_scratch4_ptr, PMC_SCRATCH4_LP, and read32().
Referenced by lp0_resume(), and power_on_main_cpu().
Definition at line 241 of file tegra_lp0_resume.c.
Referenced by clear_cpu_resets(), clrbits32(), config_core_sight(), config_mselect(), config_oscillator(), config_pllu(), config_tsc(), enable_cpu_clocks(), lp0_resume(), power_on_main_cpu(), power_on_partition(), reset(), and setbits32().
struct lp0_header __packed |
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Definition at line 30 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 84 of file tegra_lp0_resume.c.
Referenced by enable_cpu_clocks().
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Definition at line 118 of file tegra_lp0_resume.c.
Referenced by config_mselect(), and enable_cpu_clocks().
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Definition at line 89 of file tegra_lp0_resume.c.
Referenced by config_core_sight().
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Definition at line 102 of file tegra_lp0_resume.c.
Referenced by config_mselect().
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Definition at line 95 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 40 of file tegra_lp0_resume.c.
Referenced by config_oscillator(), and get_osc_freq().
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Definition at line 58 of file tegra_lp0_resume.c.
Referenced by config_pllu().
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Definition at line 67 of file tegra_lp0_resume.c.
Referenced by config_pllu().
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Definition at line 74 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 127 of file tegra_lp0_resume.c.
Referenced by clear_cpu_resets().
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Definition at line 125 of file tegra_lp0_resume.c.
Referenced by clear_cpu_resets().
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Definition at line 79 of file tegra_lp0_resume.c.
Referenced by config_core_sight().
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Definition at line 113 of file tegra_lp0_resume.c.
Referenced by config_mselect().
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Definition at line 25 of file tegra_lp0_resume.c.
Referenced by reset().
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Definition at line 35 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 150 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 162 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 153 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 170 of file tegra_lp0_resume.c.
Referenced by ram_repair().
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Definition at line 168 of file tegra_lp0_resume.c.
Referenced by ram_repair().
struct lp0_header header |
Definition at line 575 of file tegra_lp0_resume.c.
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Definition at line 214 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 212 of file tegra_lp0_resume.c.
Referenced by lp0_resume().
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Definition at line 186 of file tegra_lp0_resume.c.
Referenced by power_on_partition().
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Definition at line 200 of file tegra_lp0_resume.c.
Referenced by power_on_main_cpu().
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Definition at line 205 of file tegra_lp0_resume.c.
Referenced by config_oscillator().
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Definition at line 193 of file tegra_lp0_resume.c.
Referenced by power_on_partition().
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Definition at line 188 of file tegra_lp0_resume.c.
Referenced by power_on_partition().
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Definition at line 203 of file tegra_lp0_resume.c.
Referenced by get_wakeup_vector().
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Definition at line 195 of file tegra_lp0_resume.c.
Referenced by wakeup_on_lp().
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Definition at line 222 of file tegra_lp0_resume.c.
Referenced by config_tsc().
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Definition at line 228 of file tegra_lp0_resume.c.
Referenced by config_tsc().
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Definition at line 22 of file tegra_lp0_resume.c.
Referenced by udelay().
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Definition at line 16 of file tegra_lp0_resume.c.
Referenced by lp0_resume().