3 #ifndef _DRAMC_REGISTER_H_
4 #define _DRAMC_REGISTER_H_
8 #include <soc/addressmap.h>
672 DEFINE_BIT(TESTCHIP_DMA1_DMA_LP4MATAB_OPT, 12)
730 DEFINE_BIT(RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 29)
742 DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_START, 18)
805 DEFINE_BIT(PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22)
949 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DR_SHU_EN_PCM, 22)
950 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DPHY_RXDLY_TRACK_EN, 25)
951 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DDRPHY_FB_CK_EN_PCM, 16)
952 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_TX_TRACKING_DIS, 11)
954 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_PHYPLL2_SHU_EN_PCM, 27)
955 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_PHYPLL1_SHU_EN_PCM, 26)
958 DEFINE_BIT(SPM_POWER_ON_VAL1_SC_DR_SHORT_QUEUE_PCM, 31)
980 DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 17)
983 DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 17)
992 DEFINE_BIT(CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN, 17)
#define DEFINE_BITFIELD(name, high_bit, low_bit)
#define DEFINE_BIT(name, bit)
check_member(dramc_ao_regs, selph11, 0x42c)
static struct dramc_channel_regs *const ch
static struct emi_mpu_regs *const emi_mpu
uint32_t chn_md_pre_mask_shf
uint32_t chn_emi_regs_end
struct dramc_ao_regs_shu_rk rk[3]
uint32_t dummy_rd_wdata[4]
struct dramc_ao_regs::dramc_ao_regs_shu shu[4]
struct dramc_ao_regs_rk rk[3]
uint32_t dramc_ao_regs_end
uint32_t selfref_hwsave_flag
struct dramc_ddrphy_regs_shu_rk rk[3]
struct dramc_ddrphy_ao_regs::ddrphy_ao_shu::@927 b[2]
struct dramc_ddrphy_ao_regs::ddrphy_ao_shu shu[4]
struct dramc_ddrphy_ao_regs::@921::@923 r[3]
uint32_t misc_stberr_rk1_f
uint32_t misc_stberr_rk2_f
uint32_t dll_fine_tune[6]
struct dramc_ddrphy_ao_regs::@920 b[2]
uint32_t ca_dll_fine_tune[6]
uint32_t misc_stberr_rk0_r
uint32_t misc_stberr_rk1_r
uint32_t misc_stberr_rk0_f
uint32_t misc_stberr_rk2_r
uint32_t misc_extlb_rx[21]
uint32_t misc_ad_rx_cmd_o1
uint32_t misc_sta_extlb[3]
uint32_t misc_phy_rgs_stben_cmd
uint32_t misc_ad_rx_dq_o1
uint32_t misc_phy_rgs_cmd
uint32_t misc_phy_stben_b[2]
uint32_t misc_dq_rxdly_trro[32]
uint32_t dramc_ddrphy_nao_regs_end
uint32_t misc_ca_rxdly_trro[32]
struct dramc_ddrphy_regs_shu_rk::@919 b[2]
uint32_t dummy_rd_data[4]
uint32_t b0_stb_max_min_dly
uint32_t current_tx_setting1
uint32_t dqs_stbcaldec_cnt2
uint32_t b23_stb_dbg_info[16]
uint32_t b3_stb_max_min_dly
uint32_t b2_stb_max_min_dly
uint32_t current_tx_setting3
uint32_t b01_stb_dbg_info[16]
uint32_t current_tx_setting4
uint32_t fine_tune_dqm_cal
uint32_t dqs_stbcalinc_cnt1
uint32_t fine_tune_dq_cal
uint32_t dqs_stbcalinc_cnt2
uint32_t b1_stb_max_min_dly
uint32_t dqs_stbcaldec_cnt1
uint32_t current_tx_setting2
struct dramc_nao_regs_rk rk[3]
uint32_t r2w_page_miss_counter
uint32_t dqsg_retry_state1
uint32_t hwmrr_push2pop_cnt
struct dramc_no_regs_rk_counter rk_counter[3]
uint32_t dq1_toggle_counter_r
uint32_t freerun_26m_counter
uint32_t w2w_page_hit_counter
uint32_t r2w_page_hit_counter
uint32_t dqsg_retry_state
uint32_t dramc_nao_regs_end
uint32_t r2r_page_miss_counter
uint32_t test_abit_status4
uint32_t r2r_page_hit_counter
uint32_t read_bytes_counter
uint32_t r2w_interbank_counter
uint32_t write_bytes_counter
uint32_t dq2_toggle_counter_r
uint32_t test_abit_status2
uint32_t dq3_toggle_counter
uint32_t w2r_page_miss_counter
uint32_t dq1_toggle_counter
uint32_t testchip_dma_status[34]
uint32_t lat_counter_block_ale
uint32_t dramc_idle_counter
uint32_t r2r_interbank_counter
uint32_t max_sref_req_to_ack_latency_counter
uint32_t w2r_page_hit_counter
uint32_t w2r_interbank_counter
uint32_t lat_counter_aver
uint32_t refresh_pop_counter
uint32_t max_rk1_drs_req_to_ack_latency_counter
uint32_t dq3_toggle_counter_r
uint32_t test_abit_status3
uint32_t max_rk1_drs_long_req_to_ack_latency_counter
uint32_t w2w_page_miss_counter
uint32_t test_abit_status1
uint32_t w2w_interbank_counter
uint32_t dq0_toggle_counter
uint32_t lat_counter_cmd[8]
uint32_t dq2_toggle_counter
uint32_t dq0_toggle_counter_r
uint32_t pre_standby_counter
uint32_t pre_powerdown_counter
uint32_t act_standby_counter
uint32_t act_powerdown_counter