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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <acpi/acpigen.h>
#include <console/console.h>
#include <device/mmio.h>
#include <device/device.h>
#include <drivers/intel/pmc_mux/chip.h>
#include <intelblocks/acpi.h>
#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/pmc_ipc.h>
#include <intelblocks/rtc.h>
#include <soc/lpm.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/soc_chip.h>
#include <bootstate.h>
Go to the source code of this file.
Macros | |
#define | PMC_HID "INTC1026" |
Functions | |
static void | config_deep_sX (uint32_t offset, uint32_t mask, int sx, int enable) |
static void | config_deep_s5 (int on_ac, int on_dc) |
static void | config_deep_s3 (int on_ac, int on_dc) |
static void | config_deep_sx (uint32_t deepsx_config) |
static void | soc_pmc_enable (struct device *dev) |
static void | soc_pmc_read_resources (struct device *dev) |
static void | soc_pmc_fill_ssdt (const struct device *dev) |
static void | soc_pmc_init (struct device *dev) |
static void | pm1_enable_pwrbtn_smi (void *unused) |
BOOT_STATE_INIT_ENTRY (BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL) | |
static void | pmc_final (struct device *dev) |
Variables | |
struct device_operations | pmc_ops |
BOOT_STATE_INIT_ENTRY | ( | BS_DEV_INIT_CHIPS | , |
BS_ON_EXIT | , | ||
pm1_enable_pwrbtn_smi | , | ||
NULL | |||
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static |
Definition at line 51 of file pmc.c.
References config_deep_sX(), S3_PWRGATE_POL, S3AC_GATE_SUS, and S3DC_GATE_SUS.
Referenced by soc_pmc_enable().
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static |
Definition at line 42 of file pmc.c.
References config_deep_sX(), S4_PWRGATE_POL, S4AC_GATE_SUS, S4DC_GATE_SUS, S5_PWRGATE_POL, S5AC_GATE_SUS, and S5DC_GATE_SUS.
Referenced by soc_pmc_enable().
Definition at line 57 of file pmc.c.
References DSX_CFG, DSX_CFG_MASK, pmc_mmio_regs(), read32(), and write32().
Referenced by soc_pmc_enable().
Definition at line 27 of file pmc.c.
References BIOS_DEBUG, mask, offset, pmc_mmio_regs(), printk, read32(), and write32().
Referenced by config_deep_s3(), and config_deep_s5().
Definition at line 167 of file pmc.c.
References pmc_update_pm1_enable(), and PWRBTN_EN.
Definition at line 186 of file pmc.c.
References pmc_clear_pmcon_sts().
Definition at line 68 of file pmc.c.
References config, config_deep_s3(), config_deep_s5(), config_deep_sx(), config_of_soc, pmc_gpe_init(), pmc_set_power_failure_state(), and rtc_init().
Definition at line 97 of file pmc.c.
References acpi_device_name(), acpi_device_path(), acpi_device_scope(), ACPI_STATUS_DEVICE_HIDDEN_ON, acpigen_pop_len(), acpigen_write_device(), acpigen_write_mem32fixed(), acpigen_write_name(), acpigen_write_name_string(), acpigen_write_resourcetemplate_footer(), acpigen_write_resourcetemplate_header(), acpigen_write_scope(), acpigen_write_STA(), BIOS_INFO, device::chip_ops, CONFIG, config_of_soc, dev_path(), generate_acpi_power_engine_with_lpm(), get_supported_lpm_mask(), name, chip_operations::name, soc_pmc_lpm::num_substates, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, PMC_HID, pmc_ipc_acpi_fill_ssdt(), and printk.
Definition at line 144 of file pmc.c.
References ACPI_TIM_DIS, CONFIG, PCH_PWRM_ACPI_TMR_CTL, pmc_mmio_regs(), pmc_set_acpi_mode(), and setbits8.
Definition at line 82 of file pmc.c.
References ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, resource::base, resource::flags, IORESOURCE_ASSIGNED, IORESOURCE_FIXED, IORESOURCE_IO, KiB, resource::limit, mmio_resource, new_resource(), PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, and resource::size.
struct device_operations pmc_ops |
Definition at line 186 of file pmc.c.
Referenced by soc_enable().