4 #include <soc/addressmap.h>
10 #define DENALI_PHY_DATA ddr_phy_settings
11 #define DENALI_CTL_DATA ddr_ctl_settings
14 #define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL)
46 static size_t size_mb = 0;
size_t sdram_size_mb(void)
void sdram_init(const struct sdram_params *param)
#define FU540_DDRBUSBLOCKER
unsigned long long uint64_t
static void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr)
static void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr)
static void ux00ddr_enablevreftraining(size_t ahbregaddr)
static void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr)
static void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend)
static void ux00ddr_disableaxireadinterleave(size_t ahbregaddr)
static void ux00ddr_enablereadlevelinggate(size_t ahbregaddr)
static void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr)
static void ux00ddr_disableoptimalrmodw(size_t ahbregaddr)
static void ux00ddr_enablewriteleveling(size_t ahbregaddr)
static void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr)
static void ux00ddr_enablereadleveling(size_t ahbregaddr)
static uint64_t ux00ddr_phy_fixup(size_t ahbregaddr)
static uint32_t ux00ddr_getdramclass(size_t ahbregaddr)
static void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings)