coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <types.h>
6 #include <soc/gpio.h>
7 #include <vendorcode/google/chromeos/chromeos.h>
8 
9 /* Pad configuration in ramstage */
10 static const struct pad_config gpio_table[] = {
11  /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */
12  /* A0 : ESPI_IO0 ==> ESPI_IO_0 */
13  /* A1 : ESPI_IO1 ==> ESPI_IO_1 */
14  /* A2 : ESPI_IO2 ==> ESPI_IO_2 */
15  /* A3 : ESPI_IO3 ==> ESPI_IO_3 */
16  /* A4 : ESPI_CS# ==> ESPI_CS_L */
17  /* A5 : ESPI_ALERT0# ==> NC */
18  PAD_NC(GPP_A5, NONE),
19  /* A6 : ESPI_ALERT1# ==> SPKR_INT_L */
20  PAD_CFG_GPI(GPP_A6, NONE, DEEP),
21  /* A7 : SRCCLK_OE7# ==> WWAN_PCIE_WAKE_ODL */
22  PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, LEVEL, INVERT),
23  /* A8 : SRCCLKREQ7# ==> WWAN_RF_DISABLE_ODL */
24  PAD_CFG_GPO(GPP_A8, 1, DEEP),
25  /* A9 : ESPI_CLK ==> ESPI_CLK */
26  /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
27  /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */
28  PAD_CFG_GPO(GPP_A11, 1, DEEP),
29  /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
30  PAD_CFG_GPO(GPP_A12, 1, DEEP),
31  /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
32  PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
33  /* A14 : USB_OC1# ==> USB_C1_OC_ODL */
34  PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
35  /* A15 : USB_OC2# ==> USB_C2_OC_ODL */
36  PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
37  /* A16 : USB_OC3# ==> USB_A0_OC_ODL */
38  PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG),
39  /* A17 : DISP_MISCC ==> EN_FCAM_PWR */
40  PAD_CFG_GPO(GPP_A17, 1, DEEP),
41  /* A18 : DDSP_HPDB ==> HDMI_HPD */
42  PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
43  /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */
44  PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6),
45  /* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */
46  PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6),
47  /* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */
48  PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
49  /* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */
50  PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
51  /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
52  PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH),
53 
54  /* B0 : SOC_VID0 */
55  PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
56  /* B1 : SOC_VID1 */
57  PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
58  /* B2 : VRALERT# ==> M2_SSD_PLA_L */
59  PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG),
60  /* B3 : PROC_GP2 ==> SAR2_INT_L */
61  PAD_CFG_GPI_APIC_LOCK(GPP_B3, NONE, LEVEL, NONE, LOCK_CONFIG),
62  /* B4 : PROC_GP3 ==> SSD_PERST_L */
63  PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
64  /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */
65  PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
66  /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */
67  PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
68  /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
69  PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
70  /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
71  PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
72  /* B9 : NC */
73  PAD_NC(GPP_B9, NONE),
74  /* B10 : NC */
76  /* B11 : PMCALERT# ==> EN_PP3300_WLAN */
77  PAD_CFG_GPO(GPP_B11, 1, DEEP),
78  /* B12 : SLP_S0# ==> SLP_S0_L */
79  PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
80  /* B13 : PLTRST# ==> PLT_RST_L */
81  PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
82  /* B14 : SPKR ==> GPP_B14_STRAP */
83  PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG),
84  /* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */
85  PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG),
86  /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
87  PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
88  /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */
89  PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
90  /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
92  /* B19 : NC */
94  /* B20 : NC */
96  /* B21 : NC */
98  /* B22 : NC */
100  /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
101  PAD_NC(GPP_B23, NONE),
102 
103  /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
104  PAD_CFG_GPO(GPP_C0, 1, DEEP),
105  /* C1 : SMBDATA ==> USI_RST_L */
106  PAD_CFG_GPO(GPP_C1, 0, DEEP),
107  /* C2 : SMBALERT# ==> GPP_C2_STRAP */
108  PAD_NC(GPP_C2, NONE),
109  /* C3 : SML0CLK ==> EN_UCAM_PWR */
110  PAD_CFG_GPO(GPP_C3, 0, DEEP),
111  /* C4 : SML0DATA ==> EN_UCAM_SENR_PWR */
112  PAD_CFG_GPO(GPP_C4, 0, DEEP),
113  /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */
114  PAD_NC(GPP_C5, NONE),
115  /* C6 : SML1CLK ==> USI_REPORT_EN */
116  PAD_CFG_GPO(GPP_C6, 0, DEEP),
117  /* C7 : SML1DATA ==> USI_INT */
118  PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE),
119 
120  /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
121  PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
122  /* D1 : ISH_GP1 ==> FP_RST_ODL */
123  PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
124  /* D2 : ISH_GP2 ==> EN_FP_PWR */
125  PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
126  /* D3 : ISH_GP3 ==> WCAM_RST_L */
127  PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
128  /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
129  PAD_CFG_GPO(GPP_D4, 1, DEEP),
130  /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */
131  PAD_CFG_GPO(GPP_D5, 1, DEEP),
132  /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
133  PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
134  /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
135  PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
136  /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
137  PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
138  /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */
139  PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG),
140  /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
141  PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG),
142  /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
143  PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
144  /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
145  PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
146  /* D13 : ISH_UART0_RXD ==> CAM_PSW_L */
147  PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG),
148  /* D14 : ISH_UART0_TXD ==> SPKR_INT_L */
149  PAD_CFG_GPI_LOCK(GPP_D14, NONE, LOCK_CONFIG),
150  /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
151  PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
152  /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
153  PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG),
154  /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */
155  PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
156  /* D18 : UART1_TXD ==> SD_PE_RST_L */
157  PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG),
158  /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
159  PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
160 
161  /* E0 : see end of E group */
162  /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */
163  PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
164  /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
165  PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
166  /* E3 : PROC_GP0 ==> HPS_INT_ODL */
167  PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE),
168  /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
169  PAD_CFG_GPO(GPP_E4, 0, DEEP),
170  /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
171  PAD_CFG_GPO(GPP_E5, 1, DEEP),
172  /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
173  PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
174  /* E7 : PROC_GP1 ==> EN_HPS_PWR */
175  PAD_CFG_GPO(GPP_E7, 1, DEEP),
176  /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */
177  PAD_CFG_GPO(GPP_E8, 1, DEEP),
178  /* E9 : USB_OC0# ==> USB_C0_OC_ODL */
179  PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
180  /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */
181  PAD_CFG_GPI_LOCK(GPP_E10, NONE, LOCK_CONFIG),
182  /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */
183  PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG),
184  /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */
185  PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
186  /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
187  PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
188  /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */
189  PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
190  /* E15 : RSVD_TP ==> PCH_WP_OD */
192  /* E16 : RSVD_TP ==> WWAN_RST_L */
193  PAD_CFG_GPO(GPP_E16, 1, DEEP),
194  /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */
195  PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG),
196  /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
197  PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
198  /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
199  PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
200  /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */
201  PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
202  /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
203  PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
204  /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
205  PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
206  /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
207  PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
208  /* E0 : SATAXPCIE0 ==> WWAN_PERST_L
209  NB. Driven high here so that it is sequenced after WWAN_RST_L; a
210  PERST# signal would normally be reset by PLRST#, but here it will be
211  explicitly programmed during a power-down sequence. */
212  PAD_CFG_GPO(GPP_E0, 1, DEEP),
213 
214  /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
215  PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
216  /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */
217  PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
218  /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
219  PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
220  /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */
221  PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
222  /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
223  PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
224  /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */
225  PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
226  /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
227  PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
228  /* F7 : GPPF7_STRAP */
229  PAD_NC(GPP_F7, NONE),
230  /* F8 : NC */
231  PAD_NC(GPP_F8, NONE),
232  /* F9 : BOOTMPC ==> SLP_S0_GATE_R */
233  PAD_CFG_GPO(GPP_F9, 1, PLTRST),
234  /* F10 : GPPF10_STRAP */
235  PAD_NC(GPP_F10, DN_20K),
236  /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */
237  PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG),
238  /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */
239  PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG),
240  /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
241  PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
242  /* F14 : GSXDIN ==> TCHPAD_INT_ODL */
243  PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
244  /* F15 : GSXSRESET# ==> FPMCU_INT_L */
245  PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
246  /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
247  PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
248  /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
249  PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
250  /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
251  PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
252  /* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */
253  PAD_CFG_GPO(GPP_F19, 1, PLTRST),
254  /* F20 : EXT_PWR_GATE# ==> UCAM_RST_L */
255  PAD_CFG_GPO(GPP_F20, 0, DEEP),
256  /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L */
257  PAD_CFG_GPO(GPP_F21, 1, DEEP),
258  /* F22 : NC */
259  PAD_NC(GPP_F22, NONE),
260  /* F23 : NC */
261  PAD_NC(GPP_F23, NONE),
262 
263  /* H0 : GPPH0_BOOT_STRAP1 */
264  PAD_NC(GPP_H0, NONE),
265  /* H1 : GPPH1_BOOT_STRAP2 */
266  PAD_NC(GPP_H1, NONE),
267  /* H2 : GPPH2_BOOT_STRAP3 */
268  PAD_NC(GPP_H2, NONE),
269  /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
270  PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG),
271  /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */
272  PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
273  /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */
274  PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
275  /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */
276  PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
277  /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */
278  PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
279  /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */
280  PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
281  /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */
282  PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
283  /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
284  PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
285  /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
286  PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
287  /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */
288  PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG),
289  /* H13 : I2C7_SCL ==> EN_PP3300_SD */
290  PAD_NC_LOCK(GPP_H13, UP_20K, LOCK_CONFIG),
291  /* H14 : NC */
292  PAD_NC(GPP_H14, NONE),
293  /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
294  PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
295  /* H16 : NC */
296  PAD_NC(GPP_H16, NONE),
297  /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
298  PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
299  /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
300  PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
301  /* H19 : SRCCLKREQ4# ==> SAR1_INT_L */
302  PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
303  /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
304  PAD_CFG_GPO(GPP_H20, 1, DEEP),
305  /* H21 : IMGCLKOUT2 ==> UCAM_MCLK */
306  PAD_CFG_GPO(GPP_H21, 0, DEEP),
307  /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
308  PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
309  /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */
310  PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
311 
312  /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */
313  PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
314  /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */
315  PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
316  /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */
317  PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
318  /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */
319  PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
320  /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */
321  PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
322  /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */
323  PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
324  /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */
325  PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
326  /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */
327  PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
328 
329  /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */
330  PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
331  /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */
332  PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
333  /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */
334  PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
335  /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */
336  PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
337  /* S4 : SNDW2_CLK ==> SDW_SPKR_CLK */
338  PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
339  /* S5 : SNDW2_DATA ==> SDW_SPKR_DATA */
340  PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
341  /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */
342  PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
343  /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */
344  PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
345 
346  /* GPD0: BATLOW# ==> BATLOW_L */
347  PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
348  /* GPD1: ACPRESENT ==> PCH_ACPRESENT */
349  PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
350  /* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */
351  PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
352  /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
353  PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
354  /* GPD4: SLP_S3# ==> SLP_S3_L */
355  PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
356  /* GPD5: SLP_S4# ==> SLP_S4_L */
357  PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
358  /* GPD6: SLP_A# ==> SLP_A_L */
359  PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
360  /* GPD7: GPD7_STRAP */
361  PAD_NC(GPD7, NONE),
362  /* GPD8: SUSCLK ==> PCH_SUSCLK */
363  PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
364  /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
365  PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
366  /* GPD10: SLP_S5# ==> SLP_S5_L */
367  PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
368  /* GPD11: LANPHYC ==> WWAN_CONFIG1 */
369  PAD_CFG_GPI(GPD11, NONE, DEEP),
370 
371  /* Virtual GPIO */
372  /* Put unused Cnvi BT UART lines in NC mode since we use USB mode. */
377 
378  /* Put unused Cnvi UART0 lines in NC mode since we use USB mode. */
383 };
384 
385 /* Early pad configuration in bootblock */
386 static const struct pad_config early_gpio_table[] = {
387  /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
388  PAD_CFG_GPO(GPP_A12, 1, DEEP),
389  /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
390  PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
391  /* B4 : PROC_GP3 ==> SSD_PERST_L */
392  PAD_CFG_GPO(GPP_B4, 0, DEEP),
393  /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
394  PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
395  /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
396  PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
397  /*
398  * D1 : ISH_GP1 ==> FP_RST_ODL
399  * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
400  * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
401  * early on in bootblock, followed by enabling of power. Reset signal is deasserted
402  * later on in ramstage. Since reset signal is asserted in bootblock, it results in
403  * FPMCU not working after a S3 resume. This is a known issue.
404  */
405  PAD_CFG_GPO(GPP_D1, 0, DEEP),
406  /* D2 : ISH_GP2 ==> EN_FP_PWR */
407  PAD_CFG_GPO(GPP_D2, 1, DEEP),
408  /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
409  PAD_CFG_GPI(GPP_E13, NONE, DEEP),
410  /* E16 : RSVD_TP ==> WWAN_RST_L
411  * To meet timing constrains - drive reset low.
412  * Deasserted in ramstage.
413  */
414  PAD_CFG_GPO(GPP_E16, 0, DEEP),
415  /* E15 : RSVD_TP ==> PCH_WP_OD */
417  /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
418  PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
419  /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
420  PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
421  /* H13 : I2C7_SCL ==> EN_PP3300_SD */
422  PAD_NC(GPP_H13, UP_20K),
423 };
424 
425 const struct pad_config *__weak variant_gpio_table(size_t *num)
426 {
427  *num = ARRAY_SIZE(gpio_table);
428  return gpio_table;
429 }
430 
432 {
433  *num = 0;
434  return NULL;
435 }
436 
437 const struct pad_config *__weak variant_early_gpio_table(size_t *num)
438 {
440  return early_gpio_table;
441 }
442 
443 static const struct cros_gpio cros_gpios[] = {
444  CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
445  CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
446 };
447 
449 
451 {
452  *num = 0;
453  return NULL;
454 }
#define GPD11
#define GPP_H22
#define GPD3
#define GPP_H20
#define GPP_B6
Definition: gpio_soc_defs.h:59
#define GPP_VGPIO_20
#define GPP_H19
#define GPP_D1
#define GPD9
#define GPP_C2
#define GPP_D10
#define GPP_D8
#define GPP_D17
#define GPP_E3
#define GPP_A18
#define GPP_F21
#define GPP_F12
#define GPP_F16
#define GPP_S4
#define GPP_H15
#define GPP_H16
#define GPP_R4
#define GPP_E0
#define GPP_R7
#define GPP_F6
#define GPP_H18
#define GPP_D14
#define GPP_B1
Definition: gpio_soc_defs.h:54
#define GPP_F20
#define GPP_S0
#define GPP_F23
#define GPP_C5
#define GPP_H11
#define GPP_A14
#define GPP_B12
Definition: gpio_soc_defs.h:65
#define GPP_H17
#define GPP_D12
#define GPP_S5
#define GPP_B16
Definition: gpio_soc_defs.h:69
#define GPP_A5
#define GPP_B2
Definition: gpio_soc_defs.h:55
#define GPP_D7
#define GPP_R3
#define GPP_B13
Definition: gpio_soc_defs.h:66
#define GPP_E6
#define GPP_F0
#define GPP_D6
#define GPP_A19
#define GPP_D2
#define GPP_H12
#define GPP_H6
#define GPP_H2
#define GPP_R6
#define GPP_H9
#define GPD0
#define GPP_D9
#define GPP_R0
#define GPP_F5
#define GPP_B15
Definition: gpio_soc_defs.h:68
#define GPP_E13
#define GPP_VGPIO_8
#define GPP_H21
#define GPP_H13
#define GPP_S7
#define GPP_D11
#define GPP_H7
#define GPP_A6
#define GPP_H1
#define GPP_H14
#define GPP_D5
#define GPP_B22
Definition: gpio_soc_defs.h:75
#define GPP_A23
#define GPP_F9
#define GPP_S3
#define GPP_E14
#define GPP_E23
#define GPP_E9
#define GPP_E8
#define GPP_A7
#define GPP_E5
#define GPD7
#define GPP_B8
Definition: gpio_soc_defs.h:61
#define GPP_S1
#define GPP_B20
Definition: gpio_soc_defs.h:73
#define GPP_A20
#define GPP_A16
#define GPP_VGPIO_6
#define GPP_F1
#define GPP_F17
#define GPP_A12
#define GPP_F15
#define GPP_D4
#define GPP_C6
#define GPD2
#define GPP_F10
#define GPP_E7
#define GPP_F7
#define GPD1
#define GPP_F13
#define GPP_C4
#define GPP_D18
#define GPP_S6
#define GPP_B19
Definition: gpio_soc_defs.h:72
#define GPP_E17
#define GPP_E2
#define GPP_E19
#define GPP_H0
#define GPP_H5
#define GPP_VGPIO_19
#define GPP_R2
#define GPP_B9
Definition: gpio_soc_defs.h:62
#define GPD10
#define GPP_E18
#define GPP_F14
#define GPP_H3
#define GPP_F4
#define GPP_A8
#define GPP_D0
#define GPP_B14
Definition: gpio_soc_defs.h:67
#define GPP_B11
Definition: gpio_soc_defs.h:64
#define GPP_D13
#define GPP_B18
Definition: gpio_soc_defs.h:71
#define GPP_B5
Definition: gpio_soc_defs.h:58
#define GPP_B0
Definition: gpio_soc_defs.h:53
#define GPP_A11
#define GPP_R5
#define GPP_E20
#define GPP_A15
#define GPP_E10
#define GPP_F8
#define GPD8
#define GPP_A13
#define GPP_S2
#define GPP_A21
#define GPP_B23
Definition: gpio_soc_defs.h:76
#define GPP_E15
#define GPP_B10
Definition: gpio_soc_defs.h:63
#define GPP_E16
#define GPP_D19
#define GPP_C1
#define GPP_F2
#define GPP_E11
#define GPP_VGPIO_21
#define GPD6
#define GPP_F18
#define GPP_B3
Definition: gpio_soc_defs.h:56
#define GPP_A22
#define GPP_VGPIO_9
#define GPP_F22
#define GPP_D15
#define GPP_F11
#define GPP_B21
Definition: gpio_soc_defs.h:74
#define GPD4
#define GPP_B4
Definition: gpio_soc_defs.h:57
#define GPP_D16
#define GPP_F3
#define GPP_E22
#define GPP_H10
#define GPP_E21
#define GPP_C3
#define GPP_VGPIO_7
#define GPP_E12
#define GPP_A17
#define GPP_VGPIO_18
#define GPP_B17
Definition: gpio_soc_defs.h:70
#define GPP_E4
#define GPP_C0
#define GPD5
#define GPP_E1
#define GPP_H8
#define GPP_F19
#define GPP_H4
#define GPP_H23
#define GPP_B7
Definition: gpio_soc_defs.h:60
#define GPP_C7
#define GPP_D3
#define GPP_R1
#define ARRAY_SIZE(a)
Definition: helpers.h:12
const struct pad_config * variant_gpio_override_table(size_t *num)
Definition: gpio.c:198
const struct pad_config * variant_romstage_gpio_table(size_t *num)
Definition: gpio.c:210
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition: gpio.c:204
const struct pad_config *__weak variant_gpio_table(size_t *num)
Definition: gpio.c:406
DECLARE_WEAK_CROS_GPIOS(cros_gpios)
#define GPIO_PCH_WP
Definition: gpio.h:14
static const struct pad_config gpio_table[]
Definition: gpio.c:10
static const struct pad_config early_gpio_table[]
Definition: gpio.c:386
static const struct cros_gpio cros_gpios[]
Definition: gpio.c:443
const struct smm_save_state_ops *legacy_ops __weak
Definition: save_state.c:8
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define CROS_GPIO_DEVICE_NAME
Definition: gpio.h:14
#define PAD_CFG_NF_LOCK(pad, pull, func, lock_action)
Definition: gpio_defs.h:203
#define PAD_CFG_GPI(pad, pull, rst)
Definition: gpio_defs.h:284
#define PAD_NC_LOCK(pad, pull, lock_action)
Definition: gpio_defs.h:368
#define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, lock_action)
Definition: gpio_defs.h:352
#define PAD_CFG_GPI_LOCK(pad, pull, lock_action)
Definition: gpio_defs.h:290
#define PAD_CFG_GPO_LOCK(pad, val, lock_action)
Definition: gpio_defs.h:254
#define PAD_CFG_NF(pad, pull, rst, func)
Definition: gpio_defs.h:197
#define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, lock_action)
Definition: gpio_defs.h:383
#define PAD_CFG_GPI_INT(pad, pull, rst, trig)
Definition: gpio_defs.h:348
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition: gpio_defs.h:376
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247
#define PAD_CFG_GPI_GPIO_DRIVER_LOCK(pad, pull, lock_action)
Definition: gpio_defs.h:329
#define NULL
Definition: stddef.h:19