5 #include <soc/addressmap.h>
372 for (i = 0; i < num; i++, t++)
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
#define printk(level,...)
#define wait_us(timeout_us, condition)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
#define USB3_PCS_PHYSTATUS
struct ss_usb_phy_reg qmp_v4_usb_phy
static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout
static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], int num)
static const struct qmp_phy_init_tbl qmp_v4_usb3_tx_tbl[]
static const struct qmp_phy_init_tbl qmp_v4_usb3_rx_tbl[]
void ss_qmp_phy_init(void)
static const struct qmp_phy_init_tbl qmp_v4_usb3_serdes_tbl[]
check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010)
static const struct qmp_phy_init_tbl qmp_v4_usb3_pcs_tbl[]
static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout
static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout
static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout
#define QMP_PHY_QSERDES_RX_REG_BASE
#define QMP_PHY_PCS_REG_BASE
#define QMP_PHY_QSERDES_COM_REG_BASE
#define QMP_PHY_QSERDES_TX_REG_BASE
struct usb3_phy_pcs_reg_layout * qmp_pcs_reg
const struct qmp_phy_init_tbl * rx_tbl
const struct qmp_phy_init_tbl * serdes_tbl
const struct qmp_phy_init_tbl * tx_tbl
const struct qmp_phy_init_tbl * pcs_tbl
u32 pcs_lock_detect_config3
u32 pcs_usb3_rxeqtraining_dfe_time_s2
u32 pcs_lock_detect_config1
u32 pcs_lock_detect_config6
u32 pcs_refgen_req_config1
u32 pcs_usb3_lfps_det_high_count_val
u32 pcs_align_detect_config1
u32 pcs_power_down_control
u32 pcs_lock_detect_config2
u32 pcs_align_detect_config2
u32 com_coreclk_div_mode1
u32 com_integloop_gain1_mode0
u32 com_bias_en_clkbuflr_en
u32 com_sysclk_buf_enable
u32 com_div_frac_start1_mode0
u32 com_div_frac_start1_mode1
u32 com_ssc_step_size2_mode1
u32 com_ssc_step_size2_mode0
u32 com_coreclk_div_mode0
u32 com_div_frac_start3_mode0
u32 com_bin_vcocal_cmp_code2_mode1
u32 com_integloop_gain0_mode0
u32 com_ssc_step_size1_mode0
u32 com_bin_vcocal_hsclk_sel
u32 com_div_frac_start2_mode1
u32 com_ssc_step_size3_mode0
u32 com_div_frac_start3_mode1
u32 com_bin_vcocal_cmp_code2_mode0
u32 com_div_frac_start2_mode0
u32 com_ssc_step_size3_mode1
u32 com_cmn_rate_override
u32 com_bin_vcocal_cmp_code1_mode0
u32 com_ssc_step_size1_mode1
u32 com_bin_vcocal_cmp_code1_mode1
u32 rx_sigdet_deglitch_cntrl
u32 rx_rx_idac_tsettle_high
u32 rx_dfe_ctle_post_cal_offset
u32 rx_ucdr_fastlock_count_high
u32 rx_rx_equ_adaptor_cntrl4
u32 rx_ucdr_so_saturation_and_enable
u32 rx_ucdr_fastlock_count_low
u32 rx_rx_equ_adaptor_cntrl3
u32 rx_rx_equ_adaptor_cntrl2
u32 rx_aux_data_tcoarse_tfine
u32 rx_rx_eq_offset_adaptor_cntrl1
u32 rx_rx_idac_tsettle_low
u32 rx_ucdr_fastlock_fo_gain
u32 tx_res_code_lane_offset_tx
u32 tx_res_code_lane_offset_rx