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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include "sdram.h"
#include <types.h>
#include <device/mmio.h>
#include <delay.h>
#include "clock.h"
Go to the source code of this file.
Functions | |
static void | config_vtp (int nr) |
static void | config_sdram (const struct emif_regs *regs, int nr) |
Configure SDRAM. More... | |
static void | config_ddr_data (const struct ddr_data *data, int nr) |
Configure DDR DATA registers. More... | |
static void | config_io_ctrl (const struct ctrl_ioregs *ioregs) |
static void | config_cmd_ctrl (const struct cmd_control *cmd, int nr) |
Configure DDR CMD control registers. More... | |
static uint32_t | get_emif_rev (uint32_t base) |
static uint32_t | emif_sdram_type (uint32_t sdram_config) |
static void | ext_phy_settings_swlvl (const struct emif_regs *regs, int nr) |
static void | ext_phy_settings_hwlvl (const struct emif_regs *regs, int nr) |
static void | config_ddr_phy (const struct emif_regs *regs, int nr) |
Configure DDR PHY. More... | |
static void | set_sdram_timings (const struct emif_regs *regs, int nr) |
Set SDRAM timings. More... | |
static void | ddr_pll_config (uint32_t ddrpll_m) |
static void | enable_emif_clocks (void) |
void | config_ddr (uint32_t pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) |
Variables | |
static struct vtp_reg * | vtpreg [2] |
static struct emif_reg_struct * | emif_reg [2] |
Base address for EMIF instances. More... | |
static struct ddr_cmd_regs * | ddr_cmd_reg [2] |
Base addresses for DDR PHY cmd/data regs. More... | |
static struct ddr_data_regs * | ddr_data_reg [2] |
static struct ddr_cmdtctrl * | ioctrl_reg = {(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR} |
Base address for ddr io control instances. More... | |
struct ctrl_stat * | cstat = (struct ctrl_stat *)CTRL_BASE |
static struct ddr_ctrl * | ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR |
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Configure DDR CMD control registers.
Definition at line 117 of file sdram.c.
References cmd_control::cmd0csratio, cmd_control::cmd0iclkout, cmd_control::cmd1csratio, cmd_control::cmd1iclkout, cmd_control::cmd2csratio, cmd_control::cmd2iclkout, ddr_cmd_reg, and write32().
Referenced by config_ddr().
void config_ddr | ( | uint32_t | pll, |
const struct ctrl_ioregs * | ioregs, | ||
const struct ddr_data * | data, | ||
const struct cmd_control * | ctrl, | ||
const struct emif_regs * | regs, | ||
int | nr | ||
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Definition at line 311 of file sdram.c.
References config_cmd_ctrl(), config_ddr_data(), config_ddr_phy(), config_io_ctrl(), config_sdram(), config_vtp(), DDR_CKE_CTRL_NORMAL, ddr_pll_config(), ddr_ctrl::ddrckectrl, ddrctrl, enable_emif_clocks(), set_sdram_timings(), and write32().
Referenced by main().
Configure DDR DATA registers.
Definition at line 84 of file sdram.c.
References ddr_data::datafwsratio0, ddr_data::datagiratio0, ddr_data::datardsratio0, ddr_data::datawdsratio0, ddr_data::datawiratio0, ddr_data::datawrsratio0, ddr_data_reg, DDR_DATA_REGS_NR, and write32().
Referenced by config_ddr().
Configure DDR PHY.
Definition at line 234 of file sdram.c.
References EMIF_4D5, emif_reg_struct::emif_ddr_phy_ctrl_1, emif_reg_struct::emif_ddr_phy_ctrl_1_shdw, emif_reg, EMIF_REG_INITREF_DIS_MASK, emif_reg_struct::emif_sdram_ref_ctrl, emif_sdram_type(), EMIF_SDRAM_TYPE_DDR3, ext_phy_settings_hwlvl(), ext_phy_settings_swlvl(), get_emif_rev(), and write32().
Referenced by config_ddr().
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Definition at line 101 of file sdram.c.
References ctrl_ioregs::cm0ioctl, ddr_cmdtctrl::cm0ioctl, ctrl_ioregs::cm1ioctl, ddr_cmdtctrl::cm1ioctl, ctrl_ioregs::cm2ioctl, ddr_cmdtctrl::cm2ioctl, ctrl_ioregs::dt0ioctl, ddr_cmdtctrl::dt0ioctl, ctrl_ioregs::dt1ioctl, ddr_cmdtctrl::dt1ioctl, ioctrl_reg, and write32().
Referenced by config_ddr().
Configure SDRAM.
Definition at line 56 of file sdram.c.
References cstat, emif_reg, ctrl_stat::secure_emif_sdram_config, udelay(), and write32().
Referenced by config_ddr().
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Definition at line 41 of file sdram.c.
References read32(), VTP_CTRL_ENABLE, VTP_CTRL_READY, VTP_CTRL_START_EN, vtpreg, and write32().
Referenced by config_ddr().
Definition at line 269 of file sdram.c.
References am335x_cm_wkup, CLK_DIV_SEL, CLK_MODE_MASK, CLK_MODE_SEL, CLK_SEL_MASK, CLK_SEL_SHIFT, am335x_cm_wkup_regs::clkmode_dpll_ddr, am335x_cm_wkup_regs::clksel_dpll_ddr, DDRPLL_M2, DDRPLL_N, am335x_cm_wkup_regs::div_m2_dpll_ddr, am335x_cm_wkup_regs::idlest_dpll_ddr, PLL_BYPASS_MODE, read32(), ST_DPLL_CLK, ST_MN_BYPASS, and write32().
Referenced by config_ddr().
Definition at line 146 of file sdram.c.
References EMIF_REG_SDRAM_TYPE_MASK, and EMIF_REG_SDRAM_TYPE_SHIFT.
Referenced by config_ddr_phy().
Definition at line 302 of file sdram.c.
References am335x_cm_per, CM_MODULEMODE_ENABLED, am335x_cm_per_regs::emif, read32(), and write32().
Referenced by config_ddr().
Definition at line 174 of file sdram.c.
References emif_reg_struct::emif_ddr_ext_phy_ctrl_1, emif_reg_struct::emif_ddr_ext_phy_ctrl_1_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_22, emif_reg_struct::emif_ddr_ext_phy_ctrl_22_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_23, emif_reg_struct::emif_ddr_ext_phy_ctrl_23_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_24, emif_reg_struct::emif_ddr_ext_phy_ctrl_24_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_25, emif_reg_struct::emif_ddr_ext_phy_ctrl_25_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_26, emif_reg_struct::emif_ddr_ext_phy_ctrl_26_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_27, emif_reg_struct::emif_ddr_ext_phy_ctrl_27_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_28, emif_reg_struct::emif_ddr_ext_phy_ctrl_28_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_29, emif_reg_struct::emif_ddr_ext_phy_ctrl_29_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_30, emif_reg_struct::emif_ddr_ext_phy_ctrl_30_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_31, emif_reg_struct::emif_ddr_ext_phy_ctrl_31_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_32, emif_reg_struct::emif_ddr_ext_phy_ctrl_32_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_33, emif_reg_struct::emif_ddr_ext_phy_ctrl_33_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_34, emif_reg_struct::emif_ddr_ext_phy_ctrl_34_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_35, emif_reg_struct::emif_ddr_ext_phy_ctrl_35_shdw, emif_reg_struct::emif_ddr_ext_phy_ctrl_36, emif_reg_struct::emif_ddr_ext_phy_ctrl_36_shdw, emif_reg_struct::emif_iodft_tlgc, emif_reg, and write32().
Referenced by config_ddr_phy().
Definition at line 154 of file sdram.c.
References emif_reg_struct::emif_ddr_ext_phy_ctrl_1, EMIF_EXT_PHY_CTRL_TIMING_REG, emif_reg, and write32().
Referenced by config_ddr_phy().
Definition at line 132 of file sdram.c.
References base, emif_reg_struct::emif_mod_id_rev, EMIF_REG_MAJOR_REVISION_MASK, EMIF_REG_MAJOR_REVISION_SHIFT, and read32().
Referenced by config_ddr_phy().
Set SDRAM timings.
Definition at line 259 of file sdram.c.
References emif_reg, emif_reg_struct::emif_sdram_tim_1, emif_reg_struct::emif_sdram_tim_1_shdw, emif_reg_struct::emif_sdram_tim_2, emif_reg_struct::emif_sdram_tim_2_shdw, emif_reg_struct::emif_sdram_tim_3, emif_reg_struct::emif_sdram_tim_3_shdw, and write32().
Referenced by config_ddr().
Definition at line 36 of file sdram.c.
Referenced by config_sdram().
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Base addresses for DDR PHY cmd/data regs.
Definition at line 25 of file sdram.c.
Referenced by config_cmd_ctrl().
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Definition at line 28 of file sdram.c.
Referenced by config_ddr_data().
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Definition at line 38 of file sdram.c.
Referenced by config_ddr().
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Base address for EMIF instances.
Definition at line 19 of file sdram.c.
Referenced by config_ddr_phy(), config_sdram(), ext_phy_settings_hwlvl(), ext_phy_settings_swlvl(), and set_sdram_timings().
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Base address for ddr io control instances.
Definition at line 34 of file sdram.c.
Referenced by config_io_ctrl().
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Definition at line 13 of file sdram.c.
Referenced by config_vtp().