58 if (
regs->zq_config) {
157 uint32_t *emif_ext_phy_ctrl_base = 0;
160 ext_phy_ctrl_base = (
uint32_t *)&(
regs->emif_ddr_ext_phy_ctrl_1);
165 write32(emif_ext_phy_ctrl_base++, *ext_phy_ctrl_base);
167 write32(emif_ext_phy_ctrl_base++, *ext_phy_ctrl_base++);
180 if (
regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
static struct am335x_cm_wkup_regs *const am335x_cm_wkup
static struct am335x_cm_per_regs *const am335x_cm_per
uint32_t clkmode_dpll_ddr
Encapsulates DDR CMD control registers.
uint32_t secure_emif_sdram_config
This structure represents the DDR io control on AM33XX devices.
Encapsulates DDR DATA registers.
uint32_t emif_sdram_tim_3_shdw
uint32_t emif_ddr_ext_phy_ctrl_24_shdw
uint32_t emif_ddr_ext_phy_ctrl_33_shdw
uint32_t emif_ddr_ext_phy_ctrl_26
uint32_t emif_ddr_ext_phy_ctrl_24
uint32_t emif_ddr_ext_phy_ctrl_29
uint32_t emif_ddr_ext_phy_ctrl_29_shdw
uint32_t emif_sdram_tim_3
uint32_t emif_ddr_ext_phy_ctrl_34
uint32_t emif_sdram_ref_ctrl
uint32_t emif_ddr_phy_ctrl_1
uint32_t emif_ddr_phy_ctrl_1_shdw
uint32_t emif_ddr_ext_phy_ctrl_23_shdw
uint32_t emif_ddr_ext_phy_ctrl_1_shdw
uint32_t emif_ddr_ext_phy_ctrl_28
uint32_t emif_ddr_ext_phy_ctrl_22_shdw
uint32_t emif_ddr_ext_phy_ctrl_26_shdw
uint32_t emif_ddr_ext_phy_ctrl_23
uint32_t emif_ddr_ext_phy_ctrl_33
uint32_t emif_ddr_ext_phy_ctrl_28_shdw
uint32_t emif_sdram_tim_1
uint32_t emif_ddr_ext_phy_ctrl_27
uint32_t emif_ddr_ext_phy_ctrl_31_shdw
uint32_t emif_ddr_ext_phy_ctrl_1
uint32_t emif_ddr_ext_phy_ctrl_30
uint32_t emif_sdram_tim_1_shdw
uint32_t emif_ddr_ext_phy_ctrl_35
uint32_t emif_ddr_ext_phy_ctrl_25_shdw
uint32_t emif_ddr_ext_phy_ctrl_25
uint32_t emif_ddr_ext_phy_ctrl_36_shdw
uint32_t emif_ddr_ext_phy_ctrl_31
uint32_t emif_ddr_ext_phy_ctrl_22
uint32_t emif_sdram_tim_2_shdw
uint32_t emif_ddr_ext_phy_ctrl_32
uint32_t emif_sdram_tim_2
uint32_t emif_ddr_ext_phy_ctrl_35_shdw
uint32_t emif_ddr_ext_phy_ctrl_36
uint32_t emif_ddr_ext_phy_ctrl_34_shdw
uint32_t emif_ddr_ext_phy_ctrl_27_shdw
uint32_t emif_ddr_ext_phy_ctrl_30_shdw
uint32_t emif_ddr_ext_phy_ctrl_32_shdw
static struct emif_reg_struct * emif_reg[2]
Base address for EMIF instances.
static void config_ddr_phy(const struct emif_regs *regs, int nr)
Configure DDR PHY.
static void enable_emif_clocks(void)
static void ddr_pll_config(uint32_t ddrpll_m)
static void config_io_ctrl(const struct ctrl_ioregs *ioregs)
static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
static void config_ddr_data(const struct ddr_data *data, int nr)
Configure DDR DATA registers.
static void config_sdram(const struct emif_regs *regs, int nr)
Configure SDRAM.
static uint32_t emif_sdram_type(uint32_t sdram_config)
static void set_sdram_timings(const struct emif_regs *regs, int nr)
Set SDRAM timings.
static void config_vtp(int nr)
static struct ddr_ctrl * ddrctrl
static struct ddr_data_regs * ddr_data_reg[2]
static void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
Configure DDR CMD control registers.
static struct ddr_cmdtctrl * ioctrl_reg
Base address for ddr io control instances.
static uint32_t get_emif_rev(uint32_t base)
static struct vtp_reg * vtpreg[2]
void config_ddr(uint32_t pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr)
static struct ddr_cmd_regs * ddr_cmd_reg[2]
Base addresses for DDR PHY cmd/data regs.
#define DDR_PHY_CMD_ADDR2
#define EMIF_EXT_PHY_CTRL_TIMING_REG
#define EMIF_REG_INITREF_DIS_MASK
#define VTP_CTRL_START_EN
#define EMIF_REG_SDRAM_TYPE_MASK
#define DDR_CONTROL_BASE_ADDR
#define EMIF_REG_SDRAM_TYPE_SHIFT
#define EMIF_SDRAM_TYPE_DDR3
#define DDR_CKE_CTRL_NORMAL
#define DDR_PHY_DATA_ADDR
#define EMIF_REG_MAJOR_REVISION_SHIFT
#define EMIF_REG_MAJOR_REVISION_MASK
#define DDR_PHY_DATA_ADDR2