coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 
6 /* Pad configuration in ramstage */
7 static const struct pad_config gpio_table[] = {
8 
9  /* A11 : TOUCH_RPT_EN */
11 
12  /* C18 : AP_I2C_EMR_SDA */
14  /* C19 : AP_I2C_EMR_SCL */
16 
17  /* D12 : WCAM_RST_L */
19  /* D13 : EN_PP3300_CAMERA */
20  PAD_CFG_GPO(GPP_D13, 1, PLTRST),
21  /* D14 : EN_PP1200_CAMERA */
23  /* D15 : UCAM_RST_L */
25  /* D19 : WWAN_WLAN_COEX1 */
27  /* D20 : WWAN_WLAN_COEX2 */
29  /* D21 : WWAN_WLAN_COEX3 */
31 
32  /* E2 : CLK_24M_WCAM */
33  PAD_NC(GPP_E2, NONE),
34  /* E17 : HDMI_DDC_SCL */
36 
37  /* H6 : AP_I2C_CAM_SDA */
38  PAD_NC(GPP_H6, NONE),
39  /* H7 : AP_I2C_CAM_SCL */
40  PAD_NC(GPP_H7, NONE),
41 
42  /* S2 : DMIC1_CLK */
43  PAD_NC(GPP_S2, NONE),
44  /* S3 : DMIC1_DATA */
45  PAD_NC(GPP_S3, NONE),
46 };
47 
48 const struct pad_config *variant_override_gpio_table(size_t *num)
49 {
50  *num = ARRAY_SIZE(gpio_table);
51  return gpio_table;
52 }
#define GPP_D14
#define GPP_D12
#define GPP_H6
#define GPP_H7
#define GPP_C18
#define GPP_S3
#define GPP_E17
#define GPP_E2
#define GPP_D13
#define GPP_A11
#define GPP_C19
#define GPP_S2
#define GPP_D19
#define GPP_D15
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define GPP_D21
#define GPP_D20
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition: gpio.c:450
static const struct pad_config gpio_table[]
Definition: gpio.c:7
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247