3 #ifndef SOC_MEDIATEK_MT8195_SPM_H
4 #define SOC_MEDIATEK_MT8195_SPM_H
7 #include <soc/addressmap.h>
12 #define SPM_PROJECT_CODE 0xb16
13 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
16 #define BCLK_CG_EN_LSB (1U << 0)
22 #define PCM_CK_EN_LSB (1U << 2)
23 #define PCM_SW_RESET_LSB (1U << 15)
26 #define RG_IM_SLAVE_LSB (1U << 0)
27 #define RG_AHBMIF_APBEN_LSB (1U << 3)
28 #define RG_PCM_TIMER_EN_LSB (1U << 5)
29 #define SPM_EVENT_COUNTER_CLR_LSB (1U << 6)
30 #define RG_PCM_WDT_WAKE_LSB (1U << 9)
31 #define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11)
32 #define REG_EVENT_LOCK_EN_LSB (1U << 12)
33 #define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14)
36 #define SPM_WAKEUP_EVENT_MASK_BIT0 (1U << 0)
37 #define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B (1U << 11)
40 #define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0)
47 #define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
48 #define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
49 #define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
60 #define POWER_ON_VAL1_DEF 0x80015860
61 #define SPM_WAKEUP_EVENT_MASK_DEF 0xffffffff
62 #define SPM_BUS_PROTECT_MASK_B_DEF 0xffffffff
63 #define SPM_BUS_PROTECT2_MASK_B_DEF 0xffffffff
64 #define MD32PCM_DMA0_CON_VAL 0x0003820e
65 #define MD32PCM_DMA0_START_VAL 0x00008000
66 #define MD32PCM_CFGREG_SW_RSTN_RUN 0x1
67 #define SPM_DVFS_LEVEL_DEF 0x00000001
68 #define SPM_DVS_DFS_LEVEL_DEF 0x00010001
69 #define SPM_RESOURCE_ACK_CON0_DEF 0xffffffff
70 #define SPM_RESOURCE_ACK_CON1_DEF 0xffffffff
71 #define SPM_RESOURCE_ACK_CON2_DEF 0xffffffff
72 #define SPM_RESOURCE_ACK_CON3_DEF 0xffffffff
73 #define ARMPLL_CLK_SEL_DEF 0x3ff
74 #define SPM_SYSCLK_SETTLE 0x60fe
75 #define SPM_INIT_DONE_US 20
76 #define PCM_WDT_TIMEOUT (30 * 32768)
77 #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
85 #define ISRM_TWAM (1U << 2)
86 #define ISRM_RET_IRQ_AUX (0x3ff << 8)
87 #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
88 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
91 #define ISRS_TWAM (1U << 2)
92 #define ISRS_PCM_RETURN (1U << 3)
93 #define ISRC_TWAM ISRS_TWAM
94 #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
95 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
98 #define PCM_PWRIO_EN_R0 (1U << 0)
99 #define PCM_PWRIO_EN_R7 (1U << 7)
100 #define PCM_RF_SYNC_R0 (1U << 16)
101 #define PCM_RF_SYNC_R6 (1U << 22)
102 #define PCM_RF_SYNC_R7 (1U << 23)
105 #define PCM_SW_INT_ALL 0x3ff
972 .pwr_sta_mask = 0x1 << 11,
973 .sram_pdn_mask = 0x1 << 8,
974 .sram_ack_mask = 0x1 << 12,
978 .pwr_sta_mask = 0x1 << 13,
979 .sram_pdn_mask = 0x1 << 8,
980 .sram_ack_mask = 0x1 << 12,
984 .pwr_sta_mask = 0x1 << 12,
985 .sram_pdn_mask = 0x1 << 8,
986 .sram_ack_mask = 0x1 << 12,
990 .pwr_sta_mask = 0x1 << 14,
991 .sram_pdn_mask = 0x1 << 8,
992 .sram_ack_mask = 0x1 << 12,
996 .pwr_sta_mask = 0x1 << 17,
997 .sram_pdn_mask = 0x1 << 8,
998 .sram_ack_mask = 0x1 << 12,
1005 .pwr_sta_mask = 0x1 << 10,
1006 .sram_pdn_mask = 0x1 << 8,
1007 .sram_ack_mask = 0x1 << 12,
1011 .pwr_sta_mask = 0x1 << 8,
1012 .sram_pdn_mask = 0x1 << 8,
1013 .sram_ack_mask = 0x1 << 12,
#define DEFINE_BITFIELD(name, high_bit, low_bit)
#define DEFINE_BIT(name, bit)
check_member(mtk_spm_regs, sleep_ca15_wfi_en[3], 0xf1c)
#define SYS_TIMER_START_EN_LSB
#define SPM_DVFSRC_ENABLE_LSB
#define SPM_DVFS_FORCE_ENABLE_LSB
#define MD32PCM_CFGREG_SW_RSTN_RESET
#define REG_SYSCLK1_SRC_MD2_SRCCLKENA
static const struct power_domain_data disp[]
static struct mtk_spm_regs *const mtk_spm
static const struct power_domain_data audio[]
uint32_t dramc_dpy_clk_spm_con
u32 spm_pmsr_general_con0
u32 spm_resource_ack_con4
uint32_t pwr_status_mask_req_1
uint32_t spm_cpu2_pwr_con
uint32_t rg_module_sw_cg_0_mask_req_2
uint32_t spm_ddren_event_count_sta
uint32_t dramc_dpy_clk_sw_sel_1
uint32_t spm_power_on_val2
u32 dramc_gating_err_latch_ch0_2
u32 spm_dram_mcu_sw_con_2
uint32_t spm_bus_protect_mask_b
uint32_t dramc_mcu2_sram_con
uint32_t spm_resource_ack_con2
uint32_t rg_module_sw_cg_1_mask_req_0
uint32_t md32pcm_wakeup_sta
u32 spm_dram_mcu_sw_con_1
uint32_t spm_resource_ack_con1
uint32_t bus_protect4_rdy
uint32_t bus_protect8_rdy
u32 pcm_wdt_latch_spare_0
u32 md32pcm_cfgreg_sw_rstn
uint32_t spm_bus_protect5_mask_b
uint32_t spm_cpu3_pwr_con
uint32_t dramc_dpy_clk_sw_con_1
uint32_t ven_core1_pwr_con
u32 spm_bus_protect9_mask_b
uint32_t spm_bus_protect8_mask_b
uint32_t pwr_status_mask_req_2
uint32_t spm_bus_protect2_mask_b
uint32_t other_pwr_status
uint32_t spm_bus_protect3_mask_b
uint32_t rg_module_sw_cg_3_mask_req_1
uint32_t dpy_shu_sram_con
uint32_t spm_bus_protect6_mask_b
u32 spm_dram_mcu_sw_con_3
u32 pextp_mac_top_p0_pwr_con
uint32_t spm_vtcxo_event_count_sta
uint32_t spm_cg_check_con
uint32_t spm_dram_mcu_sta_2
uint32_t md32pcm_event_sta
uint32_t spm_mcusys_pwr_con
uint32_t spm_dvs_dfs_level
u32 spm_wakeup_event_sens
u32 spm_pmsr_general_con5
uint32_t spm_vrf18_event_count_sta
uint32_t spm_power_on_val3
uint32_t dramc_mcu_sram_con
uint32_t dramc_dpy_clk_sw_sel_2
u32 spm_dram_mcu_sw_con_4
uint32_t relay_dvfs_level
u32 dramc_gating_err_latch_ch0_0
uint32_t cam_rawc_pwr_con
uint32_t spm_bus_protect7_mask_b
uint32_t bus_protect1_rdy
uint32_t spm_sw_rst_con_clr
uint32_t spm_cpu7_pwr_con
uint32_t spm_dram_mcu_sta_1
u32 dramc_gating_err_latch_ch0_4
uint32_t spm_cpu5_pwr_con
uint32_t devapc_acp_sram_con
u32 spm_wakeup_event_ext_mask
u32 pcm_wdt_latch_spare_2
uint32_t rg_module_sw_cg_3_mask_req_2
uint32_t spm_cpu6_pwr_con
uint32_t ext_int_wakeup_req
u32 spm_pmsr_general_con3
u32 spm_dram_mcu_sw_con_0
uint32_t rg_module_sw_cg_0_mask_req_0
uint32_t spm_infra_event_count_sta
uint32_t dvfsrc_event_sta
uint32_t cam_rawa_pwr_con
u32 spm_cross_wake_m01_req
u32 dramc_gating_err_latch_ch0_3
uint32_t rg_module_sw_cg_1_mask_req_1
uint32_t dramc_dpy_clk_sw_con_0
u32 ssusb_pcie_phy_pwr_con
uint32_t rg_module_sw_cg_2_mask_req_0
uint32_t spm_cpu4_pwr_con
u32 spm_pmsr_general_con1
u32 spm_cross_wake_m02_req
uint32_t spm_ack_chk_timer_3
u32 spm_wakeup_event_mask2
uint32_t spm_bus_protect1_mask_b
uint32_t spm_resource_ack_con0
uint32_t pwr_status_mask_req_0
uint32_t debugtop_sram_con
uint32_t devapc_ifr_sram_con
uint32_t dramc_dpy_clk_sw_sel_0
uint32_t dramc_dpy_clk_sw_con_3
u32 spm_wakeup_event_clear
uint32_t rg_module_sw_cg_1_mask_req_2
uint32_t spm_apsrc_event_count_sta
uint32_t bus_protect5_rdy
u32 spm_wakeup_event_mask
uint32_t spm_dram_mcu_sw_sel_0
u32 dramc_gating_err_latch_ch0_1
uint32_t spm_cg_check_sta
u32 spm_pmsr_general_con4
u32 spm_cross_wake_m03_req
u32 dramc_gating_err_latch_ch0_5
uint32_t rg_module_sw_cg_3_mask_req_0
uint32_t dramc_dpy_clk_sw_sel_3
u32 pextp_mac_top_p1_pwr_con
u32 spm_cross_wake_m00_req
uint32_t rg_module_sw_cg_0_mask_req_1
uint32_t rg_module_sw_cg_2_mask_req_2
uint32_t spm_cpu1_pwr_con
uint32_t bus_protect6_rdy
uint32_t spm_ack_chk_sel_3
uint32_t spm_bus_protect4_mask_b
uint32_t spm_dram_mcu_sta_0
uint32_t spm_sw_rst_con_set
uint32_t spm_resource_ack_con3
uint32_t spm_dvfs_opp_sta
uint32_t ext_int_wakeup_req_clr
uint32_t spm_cputop_pwr_con
uint32_t rg_module_sw_cg_2_mask_req_1
uint32_t dramc_dpy_clk_sw_con_2
uint32_t spm_cpu0_pwr_con
uint32_t ext_int_wakeup_req_set
uint32_t spm_ack_chk_con_3
u32 dramc_gating_err_latch_spare_0
uint32_t spm_ack_chk_pc_3
uint32_t cam_rawb_pwr_con
u32 spm_pmsr_general_con2
u32 pcm_wdt_latch_spare_1
uint32_t devapc_subifr_sram_con
uint32_t bus_protect7_rdy
uint8_t reg_ufs_ddr_en_mask_b
uint8_t reg_pextp_p1_ddr_en_mask_b
uint8_t reg_bak_psri_apsrc_req_mask_b
uint8_t reg_infrasys_ddr_en_mask_b
uint8_t reg_msdc1_infra_req_mask_b
uint8_t reg_apu_vrf18_req_mask_b
uint8_t reg_apu_infra_req_mask_b
uint8_t reg_gce0_infra_req_mask_b
uint8_t reg_ufs_infra_req_mask_b
uint8_t reg_msdc0_vrf18_req_mask_b
uint8_t reg_ufs_srcclkena_mask_b
uint8_t reg_sspm_srcclkena_0_mask_b
uint8_t reg_msdc2_srcclkena_mask_b
uint8_t reg_disp0_apsrc_req_mask_b
uint8_t reg_disp3_apsrc_req_mask_b
uint32_t reg_mcusys_merge_ddr_en_mask_b
uint8_t reg_cg_check_vrf18_req_mask_b
uint8_t reg_disp1_apsrc_req_mask_b
uint8_t reg_msdc0_ddr_en_mask_b
uint8_t reg_spm_infra_req_reserved_mask_b
uint8_t reg_pextp_p1_apsrc_req_mask_b
uint8_t reg_ufs_apsrc_req_mask_b
uint8_t reg_dramc_md32_vrf18_req_mask_b
uint8_t reg_csyspwrup_req_mask
uint8_t reg_scp_ddr_en_mask_b
uint8_t reg_gce1_apsrc_req_mask_b
uint8_t reg_scp_infra_req_mask_b
uint8_t reg_msdc0_srcclkena_mask_b
uint8_t reg_disp2_apsrc_req_mask_b
uint32_t pcm_flags_cust_set
uint8_t reg_msdc2_apsrc_req_mask_b
uint8_t reg_audio_dsp_apsrc_req_mask_b
uint8_t reg_spm_vrf18_req
uint8_t reg_msdc2_vrf18_req_mask_b
uint8_t reg_pextp_p1_vrf18_req_mask_b
uint8_t reg_msdc0_infra_req_mask_b
uint8_t reg_disp3_ddr_en_mask_b
uint8_t reg_spm_vrf18_req_reserved_mask_b
uint8_t reg_gce0_apsrc_req_mask_b
uint32_t reg_wakeup_event_mask
uint8_t reg_scp_vrf18_req_mask_b
uint8_t reg_dramc_md32_infra_req_mask_b
uint8_t reg_gce1_ddr_en_mask_b
uint8_t reg_apu_srcclkena_mask_b
uint8_t reg_md_apsrc_1_sel
uint8_t reg_msdc2_infra_req_mask_b
uint8_t reg_cpueb_ddr_en_mask_b
uint8_t reg_spm_ddr_en_reserved_mask_b
uint8_t reg_sspm_infra_req_0_mask_b
uint8_t reg_bak_psri_vrf18_req_mask_b
uint8_t reg_sc_adsp2spm_wakeup_mask_b
uint8_t reg_apu_apsrc_req_mask_b
uint8_t reg_apu_ddr_en_mask_b
uint8_t reg_spm_srcclkena_reserved_mask_b
uint8_t reg_usb_ddr_en_mask_b
uint8_t reg_gce1_vrf18_req_mask_b
uint8_t reg_cpueb_infra_req_mask_b
uint32_t pcm_flags_cust_clr
uint8_t reg_conn_apsrc_sel
uint8_t reg_spm_adsp_mailbox_req
uint8_t reg_audio_dsp_infra_req_mask_b
uint8_t reg_cpueb_vrf18_req_mask_b
uint8_t reg_pextp_p1_srcclkena_mask_b
uint8_t reg_infrasys_apsrc_req_mask_b
uint8_t reg_mp1_cputop_idle_mask
uint8_t reg_audio_dsp_vrf18_req_mask_b
uint8_t reg_usb_infra_req_mask_b
uint8_t reg_pextp_p1_infra_req_mask_b
uint32_t timer_val_ramp_en
uint8_t reg_bak_psri_srcclkena_mask_b
uint8_t reg_pextp_p0_srcclkena_mask_b
uint8_t reg_usb_apsrc_req_mask_b
uint8_t reg_msdc1_vrf18_req_mask_b
uint8_t reg_pextp_p0_ddr_en_mask_b
uint8_t reg_cg_check_srcclkena_mask_b
uint8_t reg_dramc_md32_ddr_en_mask_b
uint8_t reg_msdc1_apsrc_req_mask_b
uint8_t reg_md_apsrc_0_sel
uint8_t reg_mcusys_idle_mask
uint8_t reg_usb_vrf18_req_mask_b
uint8_t reg_spm_sspm_mailbox_req
uint8_t reg_scp_apsrc_req_mask_b
uint8_t reg_usb_srcclkena_mask_b
uint8_t reg_cg_check_apsrc_req_mask_b
uint8_t reg_gce0_vrf18_req_mask_b
uint8_t reg_audio_dsp_ddr_en_mask_b
uint8_t reg_pextp_p0_infra_req_mask_b
uint8_t reg_sspm_vrf18_req_0_mask_b
uint8_t reg_gce1_infra_req_mask_b
uint8_t reg_ufs_vrf18_req_mask_b
uint32_t pcm_flags1_cust_set
uint8_t reg_cg_check_ddr_en_mask_b
uint32_t reg_mcusys_merge_apsrc_req_mask_b
uint32_t pcm_flags1_cust_clr
uint8_t reg_sc_sw2spm_wakeup_mask_b
uint8_t reg_disp2_ddr_en_mask_b
uint8_t reg_spm_ddr_en_req
uint8_t reg_msdc1_srcclkena_mask_b
uint8_t reg_csyspwrup_ack_mask
uint8_t reg_pextp_p0_vrf18_req_mask_b
uint8_t reg_msdc1_ddr_en_mask_b
uint8_t reg_sc_sspm2spm_wakeup_mask_b
uint8_t reg_disp0_ddr_en_mask_b
uint32_t reg_ext_wakeup_event_mask
uint8_t reg_sc_scp2spm_wakeup_mask_b
uint32_t timer_val_ramp_en_sec
uint8_t reg_cpueb_apsrc_req_mask_b
uint8_t reg_bak_psri_ddr_en_mask_b
uint8_t reg_disp1_ddr_en_mask_b
uint8_t reg_msdc0_apsrc_req_mask_b
uint8_t reg_sspm_apsrc_req_0_mask_b
uint8_t reg_scp_srcclkena_mask_b
uint8_t reg_bak_psri_infra_req_mask_b
uint8_t reg_spm_sw_mailbox_req
uint8_t reg_spm_infra_req
uint8_t reg_spm_apsrc_req
uint8_t reg_msdc2_ddr_en_mask_b
uint8_t reg_dvfsrc_event_trigger_mask_b
uint8_t reg_sspm_ddr_en_0_mask_b
uint8_t reg_spm_apsrc_req_reserved_mask_b
uint8_t reg_cpueb_srcclkena_mask_b
uint8_t reg_gce0_ddr_en_mask_b
uint8_t reg_audio_dsp_srcclkena_mask_b
uint8_t reg_pextp_p0_apsrc_req_mask_b
uint8_t reg_spm_scp_mailbox_req
uint8_t reg_mp0_cputop_idle_mask