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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET 16 |
#define | ASPM_LTR_L12_THRESHOLD_VALUE_MASK (0x3ff << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET) |
#define | ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29 |
#define | ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET) |
#define | PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003 |
#define | PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003 |
Enumerations | |
enum | aspm_type { PCIE_ASPM_NONE = 0 , PCIE_ASPM_L0S = 1 , PCIE_ASPM_L1 = 2 , PCIE_ASPM_BOTH = 3 } |
Functions | |
void | pciexp_scan_bus (struct bus *bus, unsigned int min_devfn, unsigned int max_devfn) |
void | pciexp_scan_bridge (struct device *dev) |
void | pciexp_hotplug_scan_bridge (struct device *dev) |
unsigned int | pciexp_find_extended_cap (const struct device *dev, unsigned int cap) |
unsigned int | pciexp_find_next_extended_cap (const struct device *dev, unsigned int cap, unsigned int offset) |
static bool | pciexp_is_downstream_port (int type) |
bool | pciexp_get_ltr_max_latencies (struct device *dev, u16 *max_snoop, u16 *max_nosnoop) |
Variables | |
struct device_operations | default_pciexp_ops_bus |
struct device_operations | default_pciexp_hotplug_ops_bus |
#define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET) |
#define ASPM_LTR_L12_THRESHOLD_VALUE_MASK (0x3ff << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET) |
enum aspm_type |
Definition at line 39 of file pciexp_device.c.
References PCIE_EXT_CAP_OFFSET, and pciexp_get_ext_cap_offset().
Referenced by get_rebar_offset(), lv2_enable_ltr(), pciexp_config_L1_sub_state(), and pciexp_configure_ltr().
unsigned int pciexp_find_next_extended_cap | ( | const struct device * | dev, |
unsigned int | cap, | ||
unsigned int | offset | ||
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Definition at line 32 of file pciexp_device.c.
References pci_read_config32(), and pciexp_get_ext_cap_offset().
Definition at line 194 of file pciexp_device.c.
References device::bus, bus::dev, DEVICE_PATH_PCI, device::ops, device_operations::ops_pci, device::path, and device_path::type.
Referenced by lv2_enable_ltr(), and pciexp_configure_ltr().
Definition at line 591 of file pciexp_device.c.
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inlinestatic |
Definition at line 37 of file pciexp.h.
References PCI_EXP_TYPE_DOWNSTREAM, PCI_EXP_TYPE_PCIE_BRIDGE, PCI_EXP_TYPE_ROOT_PORT, and type.
Referenced by pci_bus_only_one_child().
Definition at line 534 of file pciexp_device.c.
Definition at line 514 of file pciexp_device.c.
References bus::children, bus::dev, pci_path::devfn, DEVICE_PATH_PCI, device::path, device_path::pci, pci_scan_bus(), pciexp_enable_ltr(), pciexp_tune_dev(), device::sibling, and device_path::type.
Referenced by byt_pciexp_scan_bridge().
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extern |
Definition at line 591 of file pciexp_device.c.
Referenced by get_pci_bridge_ops().
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extern |
Definition at line 534 of file pciexp_device.c.
Referenced by get_pci_bridge_ops().