coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
pciexp.h
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1 #ifndef DEVICE_PCIEXP_H
2 #define DEVICE_PCIEXP_H
3 /* (c) 2005 Linux Networx GPL see COPYING for details */
4 
5 enum aspm_type {
10 };
11 
12 #define ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET 16
13 #define ASPM_LTR_L12_THRESHOLD_VALUE_MASK (0x3ff << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET)
14 #define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29
15 #define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)
16 
17 /* Latency tolerance reporting, max non-snoop latency value 3.14ms */
18 #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003
19 /* Latency tolerance reporting, max snoop latency value 3.14ms */
20 #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003
21 
22 void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
23  unsigned int max_devfn);
24 
25 void pciexp_scan_bridge(struct device *dev);
26 
28 
29 void pciexp_hotplug_scan_bridge(struct device *dev);
30 
32 
33 unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap);
34 unsigned int pciexp_find_next_extended_cap(const struct device *dev, unsigned int cap,
35  unsigned int offset);
36 
37 static inline bool pciexp_is_downstream_port(int type)
38 {
39  return type == PCI_EXP_TYPE_ROOT_PORT ||
42 }
43 
44 bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop);
45 
46 #endif /* DEVICE_PCIEXP_H */
static size_t offset
Definition: flashconsole.c:16
unsigned int type
Definition: edid.c:57
#define PCI_EXP_TYPE_ROOT_PORT
Definition: pci_def.h:383
#define PCI_EXP_TYPE_PCIE_BRIDGE
Definition: pci_def.h:387
#define PCI_EXP_TYPE_DOWNSTREAM
Definition: pci_def.h:385
static bool pciexp_is_downstream_port(int type)
Definition: pciexp.h:37
unsigned int pciexp_find_next_extended_cap(const struct device *dev, unsigned int cap, unsigned int offset)
Definition: pciexp_device.c:32
struct device_operations default_pciexp_ops_bus
unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap)
Definition: pciexp_device.c:39
void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn)
struct device_operations default_pciexp_hotplug_ops_bus
aspm_type
Definition: pciexp.h:5
@ PCIE_ASPM_L1
Definition: pciexp.h:8
@ PCIE_ASPM_L0S
Definition: pciexp.h:7
@ PCIE_ASPM_BOTH
Definition: pciexp.h:9
@ PCIE_ASPM_NONE
Definition: pciexp.h:6
void pciexp_hotplug_scan_bridge(struct device *dev)
void pciexp_scan_bridge(struct device *dev)
bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop)
uint16_t u16
Definition: stdint.h:48
Definition: device.h:76
Definition: device.h:107