coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
reset.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <
device/pci_ops.h
>
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#include <
cf9_reset.h
>
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#include <reset.h>
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#define HT_INIT_CONTROL 0x6c
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#define HTIC_ColdR_Detect (1<<4)
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#define HTIC_BIOSR_Detect (1<<5)
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#define HTIC_INIT_Detect (1<<6)
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void
cf9_reset_prepare
(
void
)
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{
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u32
htic;
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htic =
pci_s_read_config32
(
PCI_DEV
(0, 0x18, 0),
HT_INIT_CONTROL
);
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htic &= ~
HTIC_BIOSR_Detect
;
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pci_s_write_config32
(
PCI_DEV
(0, 0x18, 0),
HT_INIT_CONTROL
, htic);
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}
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void
do_board_reset
(
void
)
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{
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system_reset
();
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}
system_reset
void system_reset(void)
Definition:
cf9_reset.c:37
cf9_reset.h
pci_ops.h
do_board_reset
void do_board_reset(void)
Definition:
reset.c:8
pci_s_read_config32
static __always_inline uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
Definition:
pci_io_cfg.h:92
pci_s_write_config32
static __always_inline void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
Definition:
pci_io_cfg.h:110
PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN)
Definition:
pci_type.h:14
cf9_reset_prepare
void cf9_reset_prepare(void)
Definition:
reset.c:20
HT_INIT_CONTROL
#define HT_INIT_CONTROL
Definition:
reset.c:10
HTIC_BIOSR_Detect
#define HTIC_BIOSR_Detect
Definition:
reset.c:12
u32
uint32_t u32
Definition:
stdint.h:51
src
southbridge
amd
pi
hudson
reset.c
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