coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Macros | Functions | Variables
pcie.c File Reference
#include <commonlib/stdlib.h>
#include <console/console.h>
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/resource.h>
#include <delay.h>
#include <lib.h>
#include <soc/addressmap.h>
#include <soc/early_init.h>
#include <soc/pcie.h>
#include <soc/pcie_common.h>
#include <soc/soc_chip.h>
#include <stdlib.h>
#include <types.h>
Include dependency graph for pcie.c:

Go to the source code of this file.

Macros

#define PCIE_SETTING_REG   0x80
 
#define PCIE_PCI_IDS_1   0x9c
 
#define PCI_CLASS(class)   ((class) << 8)
 
#define PCIE_RC_MODE   BIT(0)
 
#define PCIE_CFGNUM_REG   0x140
 
#define PCIE_CFG_DEVFN(devfn)   ((devfn) & GENMASK(7, 0))
 
#define PCIE_CFG_BUS(bus)   (((bus) << 8) & GENMASK(15, 8))
 
#define PCIE_CFG_OFFSET_ADDR   0x1000
 
#define PCIE_CFG_HEADER(bus, devfn)    (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
 
#define PCIE_RST_CTRL_REG   0x148
 
#define PCIE_MAC_RSTB   BIT(0)
 
#define PCIE_PHY_RSTB   BIT(1)
 
#define PCIE_BRG_RSTB   BIT(2)
 
#define PCIE_PE_RSTB   BIT(3)
 
#define PCIE_LTSSM_STATUS_REG   0x150
 
#define PCIE_LTSSM_STATE(val)   (((val) >> 24) & 0x1f)
 
#define PCIE_LINK_STATUS_REG   0x154
 
#define PCIE_CTRL_LINKUP   BIT(8)
 
#define PCI_NUM_INTX   4
 
#define PCIE_INT_ENABLE_REG   0x180
 
#define PCIE_INTX_SHIFT   24
 
#define PCIE_INTX_ENABLE    GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
 
#define PCIE_TRANS_TABLE_BASE_REG   0x800
 
#define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 
#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET   0x8
 
#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET   0xc
 
#define PCIE_ATR_TRSL_PARAM_OFFSET   0x10
 
#define PCIE_ATR_TLB_SET_OFFSET   0x20
 
#define PCIE_MAX_TRANS_TABLES   8
 
#define PCIE_ATR_EN   BIT(0)
 
#define PCIE_ATR_SIZE(size)    (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
 
#define PCIE_ATR_ID(id)   ((id) & GENMASK(3, 0))
 
#define PCIE_ATR_TYPE_MEM   PCIE_ATR_ID(0)
 
#define PCIE_ATR_TYPE_IO   PCIE_ATR_ID(1)
 
#define PCIE_ATR_TLP_TYPE(type)   (((type) << 16) & GENMASK(18, 16))
 
#define PCIE_ATR_TLP_TYPE_MEM   PCIE_ATR_TLP_TYPE(0)
 
#define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
 

Functions

static uintptr_t mtk_pcie_get_controller_base (pci_devfn_t devfn)
 
volatile union pci_bank * pci_map_bus (pci_devfn_t dev)
 
static int mtk_pcie_set_trans_window (struct device *dev, uintptr_t table, const struct mtk_pcie_mmio_res *mmio_res)
 
static void mtk_pcie_domain_new_res (struct device *dev, unsigned int index, const struct mtk_pcie_mmio_res *mmio_res)
 
void mtk_pcie_domain_read_resources (struct device *dev)
 
void mtk_pcie_domain_set_resources (struct device *dev)
 
void mtk_pcie_domain_enable (struct device *dev)
 

Variables

static const char *const ltssm_str []
 

Macro Definition Documentation

◆ PCI_CLASS

#define PCI_CLASS (   class)    ((class) << 8)

Definition at line 23 of file pcie.c.

◆ PCI_NUM_INTX

#define PCI_NUM_INTX   4

Definition at line 45 of file pcie.c.

◆ PCIE_ATR_EN

#define PCIE_ATR_EN   BIT(0)

Definition at line 59 of file pcie.c.

◆ PCIE_ATR_ID

#define PCIE_ATR_ID (   id)    ((id) & GENMASK(3, 0))

Definition at line 62 of file pcie.c.

◆ PCIE_ATR_SIZE

#define PCIE_ATR_SIZE (   size)     (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)

Definition at line 60 of file pcie.c.

◆ PCIE_ATR_SRC_ADDR_MSB_OFFSET

#define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4

Definition at line 52 of file pcie.c.

◆ PCIE_ATR_TLB_SET_OFFSET

#define PCIE_ATR_TLB_SET_OFFSET   0x20

Definition at line 56 of file pcie.c.

◆ PCIE_ATR_TLP_TYPE

#define PCIE_ATR_TLP_TYPE (   type)    (((type) << 16) & GENMASK(18, 16))

Definition at line 65 of file pcie.c.

◆ PCIE_ATR_TLP_TYPE_IO

#define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)

Definition at line 67 of file pcie.c.

◆ PCIE_ATR_TLP_TYPE_MEM

#define PCIE_ATR_TLP_TYPE_MEM   PCIE_ATR_TLP_TYPE(0)

Definition at line 66 of file pcie.c.

◆ PCIE_ATR_TRSL_ADDR_LSB_OFFSET

#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET   0x8

Definition at line 53 of file pcie.c.

◆ PCIE_ATR_TRSL_ADDR_MSB_OFFSET

#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET   0xc

Definition at line 54 of file pcie.c.

◆ PCIE_ATR_TRSL_PARAM_OFFSET

#define PCIE_ATR_TRSL_PARAM_OFFSET   0x10

Definition at line 55 of file pcie.c.

◆ PCIE_ATR_TYPE_IO

#define PCIE_ATR_TYPE_IO   PCIE_ATR_ID(1)

Definition at line 64 of file pcie.c.

◆ PCIE_ATR_TYPE_MEM

#define PCIE_ATR_TYPE_MEM   PCIE_ATR_ID(0)

Definition at line 63 of file pcie.c.

◆ PCIE_BRG_RSTB

#define PCIE_BRG_RSTB   BIT(2)

Definition at line 36 of file pcie.c.

◆ PCIE_CFG_BUS

#define PCIE_CFG_BUS (   bus)    (((bus) << 8) & GENMASK(15, 8))

Definition at line 28 of file pcie.c.

◆ PCIE_CFG_DEVFN

#define PCIE_CFG_DEVFN (   devfn)    ((devfn) & GENMASK(7, 0))

Definition at line 27 of file pcie.c.

◆ PCIE_CFG_HEADER

#define PCIE_CFG_HEADER (   bus,
  devfn 
)     (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))

Definition at line 30 of file pcie.c.

◆ PCIE_CFG_OFFSET_ADDR

#define PCIE_CFG_OFFSET_ADDR   0x1000

Definition at line 29 of file pcie.c.

◆ PCIE_CFGNUM_REG

#define PCIE_CFGNUM_REG   0x140

Definition at line 26 of file pcie.c.

◆ PCIE_CTRL_LINKUP

#define PCIE_CTRL_LINKUP   BIT(8)

Definition at line 43 of file pcie.c.

◆ PCIE_INT_ENABLE_REG

#define PCIE_INT_ENABLE_REG   0x180

Definition at line 46 of file pcie.c.

◆ PCIE_INTX_ENABLE

#define PCIE_INTX_ENABLE    GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)

Definition at line 48 of file pcie.c.

◆ PCIE_INTX_SHIFT

#define PCIE_INTX_SHIFT   24

Definition at line 47 of file pcie.c.

◆ PCIE_LINK_STATUS_REG

#define PCIE_LINK_STATUS_REG   0x154

Definition at line 42 of file pcie.c.

◆ PCIE_LTSSM_STATE

#define PCIE_LTSSM_STATE (   val)    (((val) >> 24) & 0x1f)

Definition at line 40 of file pcie.c.

◆ PCIE_LTSSM_STATUS_REG

#define PCIE_LTSSM_STATUS_REG   0x150

Definition at line 39 of file pcie.c.

◆ PCIE_MAC_RSTB

#define PCIE_MAC_RSTB   BIT(0)

Definition at line 34 of file pcie.c.

◆ PCIE_MAX_TRANS_TABLES

#define PCIE_MAX_TRANS_TABLES   8

Definition at line 58 of file pcie.c.

◆ PCIE_PCI_IDS_1

#define PCIE_PCI_IDS_1   0x9c

Definition at line 22 of file pcie.c.

◆ PCIE_PE_RSTB

#define PCIE_PE_RSTB   BIT(3)

Definition at line 37 of file pcie.c.

◆ PCIE_PHY_RSTB

#define PCIE_PHY_RSTB   BIT(1)

Definition at line 35 of file pcie.c.

◆ PCIE_RC_MODE

#define PCIE_RC_MODE   BIT(0)

Definition at line 24 of file pcie.c.

◆ PCIE_RST_CTRL_REG

#define PCIE_RST_CTRL_REG   0x148

Definition at line 33 of file pcie.c.

◆ PCIE_SETTING_REG

#define PCIE_SETTING_REG   0x80

Definition at line 21 of file pcie.c.

◆ PCIE_TRANS_TABLE_BASE_REG

#define PCIE_TRANS_TABLE_BASE_REG   0x800

Definition at line 51 of file pcie.c.

Function Documentation

◆ mtk_pcie_domain_enable()

void mtk_pcie_domain_enable ( struct device *  dev)

Definition at line 213 of file pcie.c.

References ARRAY_SIZE, mtk_pcie_config::base, BIOS_DEBUG, BIOS_ERR, BIOS_INFO, BIOS_WARNING, config, config_of(), early_init_get_elapsed_time_us(), EARLY_INIT_PCIE, GENMASK, ltssm_str, mdelay(), mtk_pcie_reset(), PCI_CLASS, PCI_CLASS_BRIDGE_PCI, PCIE_CTRL_LINKUP, PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE, PCIE_LINK_STATUS_REG, PCIE_LTSSM_STATE, PCIE_LTSSM_STATUS_REG, PCIE_PCI_IDS_1, PCIE_RC_MODE, PCIE_RST_CTRL_REG, PCIE_SETTING_REG, printk, read32p(), retry, udelay(), val, and write32p().

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◆ mtk_pcie_domain_new_res()

static void mtk_pcie_domain_new_res ( struct device *  dev,
unsigned int  index,
const struct mtk_pcie_mmio_res *  mmio_res 
)
static

Definition at line 166 of file pcie.c.

References resource::base, resource::flags, resource::index, IORESOURCE_ASSIGNED, IORESOURCE_SUBTRACTIVE, resource::limit, mmio_res, new_resource(), and resource::size.

Referenced by mtk_pcie_domain_read_resources().

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◆ mtk_pcie_domain_read_resources()

void mtk_pcie_domain_read_resources ( struct device *  dev)

Definition at line 181 of file pcie.c.

References config, config_of(), IOINDEX_SUBTRACTIVE, mtk_pcie_config::mmio_res_io, mtk_pcie_config::mmio_res_mem, and mtk_pcie_domain_new_res().

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◆ mtk_pcie_domain_set_resources()

void mtk_pcie_domain_set_resources ( struct device *  dev)

Definition at line 193 of file pcie.c.

References mtk_pcie_config::base, BIOS_ERR, config, config_of(), mtk_pcie_config::mmio_res_io, mtk_pcie_config::mmio_res_mem, mtk_pcie_set_trans_window(), pci_domain_set_resources(), PCIE_ATR_TLB_SET_OFFSET, PCIE_TRANS_TABLE_BASE_REG, and printk.

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◆ mtk_pcie_get_controller_base()

static uintptr_t mtk_pcie_get_controller_base ( pci_devfn_t  devfn)
static

Definition at line 100 of file pcie.c.

References base, config, config_of(), and pcidev_path_on_root().

Referenced by pci_map_bus().

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◆ mtk_pcie_set_trans_window()

static int mtk_pcie_set_trans_window ( struct device *  dev,
uintptr_t  table,
const struct mtk_pcie_mmio_res *  mmio_res 
)
static

Definition at line 130 of file pcie.c.

References __fls(), BIOS_ERR, BIOS_INFO, IORESOURCE_IO, IORESOURCE_MEM, mmio_res, PCIE_ATR_SIZE, PCIE_ATR_SRC_ADDR_MSB_OFFSET, PCIE_ATR_TLP_TYPE_IO, PCIE_ATR_TLP_TYPE_MEM, PCIE_ATR_TRSL_ADDR_LSB_OFFSET, PCIE_ATR_TRSL_ADDR_MSB_OFFSET, PCIE_ATR_TRSL_PARAM_OFFSET, PCIE_ATR_TYPE_IO, PCIE_ATR_TYPE_MEM, printk, resource::size, and write32p().

Referenced by mtk_pcie_domain_set_resources().

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◆ pci_map_bus()

volatile union pci_bank* pci_map_bus ( pci_devfn_t  dev)

Definition at line 115 of file pcie.c.

References base, mtk_pcie_get_controller_base(), PCI_DEV2DEVFN, PCI_DEV2SEGBUS, PCIE_CFG_HEADER, PCIE_CFG_OFFSET_ADDR, PCIE_CFGNUM_REG, val, and write32p().

Referenced by pci_mmio_config16_addr(), pci_mmio_config32_addr(), pci_mmio_config8_addr(), pci_s_read_config16(), pci_s_read_config32(), pci_s_read_config8(), pci_s_write_config16(), pci_s_write_config32(), and pci_s_write_config8().

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Variable Documentation

◆ ltssm_str

const char* const ltssm_str[]
static
Initial value:
= {
"detect.quiet",
"detect.active",
"polling.active",
"polling.compliance",
"polling.configuration",
"config.linkwidthstart",
"config.linkwidthaccept",
"config.lanenumwait",
"config.lanenumaccept",
"config.complete",
"config.idle",
"recovery.receiverlock",
"recovery.equalization",
"recovery.speed",
"recovery.receiverconfig",
"recovery.idle",
"L0",
"L0s",
"L1.entry",
"L1.idle",
"L2.idle",
"L2.transmitwake",
"disable",
"loopback.entry",
"loopback.active",
"loopback.exit",
"hotreset",
}

Definition at line 70 of file pcie.c.

Referenced by mtk_pcie_domain_enable().