coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <bootstate.h>
6 #include <fw_config.h>
7 
8 /* Pad configuration in ramstage */
9 static const struct pad_config gpio_table[] = {
10  /* A10 : WWAN_EN */
11  PAD_CFG_GPO(GPP_A10, 1, PWROK),
12  /* A11 : TOUCH_RPT_EN ==> NC */
14 
15  /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL */
16  PAD_CFG_GPO(GPP_B7, 1, DEEP),
17 
18  /* C18 : AP_I2C_EMR_SDA ==> NC */
20  /* C19 : AP_I2C_EMR_SCL ==> NC */
22  /* C22 : UART2_RTS_N ==> NC */
24 
25  /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */
26  PAD_CFG_GPO(GPP_D0, 1, DEEP),
27  /* D12 : WCAM_RST_L ==> NC */
29  /* D13 : EN_PP2800_CAMERA ==> NC */
31  /* D14 : EN_PP1200_CAMERA ==> NC */
33  /* D15 : UCAM_RST_L ==> NC */
35  /* D19 : WWAN_WLAN_COEX1 ==> TP */
37  /* D20 : WWAN_WLAN_COEX2 ==> TP */
39  /* D21 : WWAN_WLAN_COEX3 ==> TP */
41 
42  /* E1 : EMR_RESET_L ==> NC */
43  PAD_NC(GPP_E1, NONE),
44  /* E2 : CLK_24M_WCAM ==> NC */
45  PAD_NC(GPP_E2, NONE),
46  /* E5 : AP_SUB_IO_2 ==> TP */
47  PAD_NC(GPP_E5, NONE),
48  /* E10 : GPP_E10/SML_DATA0 ==> NC */
50 
51  /* G0 : SD_CMD ==> NC */
52  PAD_NC(GPP_G0, NONE),
53  /* G1 : SD_DATA0 ==> NC */
54  PAD_NC(GPP_G1, NONE),
55  /* G2 : SD_DATA1 ==> NC */
56  PAD_NC(GPP_G2, NONE),
57  /* G3 : SD_DATA2 ==> NC */
58  PAD_NC(GPP_G3, NONE),
59  /* G4 : SD_DATA3 ==> NC */
60  PAD_NC(GPP_G4, NONE),
61  /* G5 : SD_CD_ODL ==> NC */
62  PAD_NC(GPP_G5, NONE),
63  /* G6 : SD_CLK ==> NC */
64  PAD_NC(GPP_G6, NONE),
65  /* G7 : SD_SDIO_WP ==> NC */
66  PAD_NC(GPP_G7, NONE),
67 
68  /* H1 : EN_PP3300_SD_U ==> NC */
69  PAD_NC(GPP_H1, NONE),
70  /* H17 : WWAN_RST_L */
71  PAD_CFG_GPO(GPP_H17, 0, PLTRST),
72 };
73 
74 static const struct pad_config lte_disable_pads[] = {
76  PAD_NC(GPP_D0, NONE),
78 };
79 
80 const struct pad_config *variant_override_gpio_table(size_t *num)
81 {
82  *num = ARRAY_SIZE(gpio_table);
83  return gpio_table;
84 }
85 
86 static void fw_config_handle(void *unused)
87 {
88  if (!fw_config_probe(FW_CONFIG(LTE, LTE_PRESENT)))
90 }
#define GPP_D14
#define GPP_H17
#define GPP_D12
#define GPP_C22
#define GPP_H1
#define GPP_C18
#define GPP_E5
#define GPP_E2
#define GPP_A10
#define GPP_D0
#define GPP_D13
#define GPP_A11
#define GPP_E10
#define GPP_C19
#define GPP_D19
#define GPP_D15
#define GPP_E1
#define GPP_B7
Definition: gpio_soc_defs.h:60
@ BS_DEV_ENABLE
Definition: bootstate.h:82
@ BS_ON_ENTRY
Definition: bootstate.h:95
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define GPP_G1
Definition: gpio_soc_defs.h:89
#define GPP_G7
Definition: gpio_soc_defs.h:95
#define GPP_G4
Definition: gpio_soc_defs.h:92
#define GPP_G2
Definition: gpio_soc_defs.h:90
#define GPP_D21
#define GPP_G6
Definition: gpio_soc_defs.h:94
#define GPP_G0
Definition: gpio_soc_defs.h:88
#define GPP_D20
#define GPP_G3
Definition: gpio_soc_defs.h:91
#define GPP_G5
Definition: gpio_soc_defs.h:93
#define FW_CONFIG(__field, __option)
Definition: fw_config.h:28
bool fw_config_probe(const struct fw_config *match)
Definition: fw_config.c:62
const struct pad_config *__weak variant_override_gpio_table(size_t *num)
Definition: gpio.c:450
static const struct pad_config lte_disable_pads[]
Definition: gpio.c:74
static const struct pad_config gpio_table[]
Definition: gpio.c:9
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL)
static void fw_config_handle(void *unused)
Definition: gpio.c:86
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition: gpio.c:307
#define PAD_NC(pin)
Definition: gpio_defs.h:263
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247
#define NULL
Definition: stddef.h:19
uint16_t unused
Definition: padconfig.h:13