coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
uart.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <soc/uart.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 
8 static void cavium_uart_init(struct device *dev)
9 {
10  const u8 fn = PCI_FUNC(dev->path.pci.devfn);
11 
12  /* Calling uart_setup with no baudrate will do minimal HW init
13  * enough for the kernel to not panic */
14  if (!uart_is_enabled(fn))
15  uart_setup(fn, 0);
16 }
17 
18 static struct device_operations device_ops = {
20 };
21 
22 static const struct pci_driver soc_cavium_uart __pci_driver = {
23  .ops = &device_ops,
24  .vendor = PCI_VENDOR_CAVIUM,
26 };
27 
29  CHIP_NAME("Cavium ThunderX UART")
30 };
#define CHIP_NAME(X)
Definition: device.h:32
#define PCI_FUNC(devfn)
Definition: pci_def.h:550
#define PCI_DID_CAVIUM_THUNDERX_UART
Definition: pci_ids.h:139
#define PCI_VENDOR_CAVIUM
Definition: pci_ids.h:138
int uart_setup(const size_t bus, int baudrate)
Setup UART with desired BAUD rate in 8N1, no parity mode.
Definition: uart.c:141
int uart_is_enabled(const size_t bus)
Returns the UART state.
Definition: uart.c:120
static struct device_operations device_ops
Definition: uart.c:18
static const struct pci_driver soc_cavium_uart __pci_driver
Definition: uart.c:22
struct chip_operations soc_cavium_common_pci_ops
Definition: uart.c:28
static void cavium_uart_init(struct device *dev)
Definition: uart.c:8
uint8_t u8
Definition: stdint.h:45
void(* init)(struct device *dev)
Definition: device.h:42
struct pci_path pci
Definition: path.h:116
Definition: device.h:107
struct device_path path
Definition: device.h:115
unsigned int devfn
Definition: path.h:54