coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <
gpio.h
>
4
#include "include/gpio.h"
5
6
/*
7
* TODO: Vendor configures many NC pads as _TERM_GPO. Why?
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* - On direction: Are some of these comments illusory? At least some pads
9
* are bidirectional on the other side of the GPIO.
10
*/
11
/* NB: Do not reconfigure pads used by Optimus, their assertion state may be lost */
12
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/*
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* TODO: Newgate-SLS and Rayleigh-SLS have PCH-H and use the same ProgramGPIOPei module.
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* The GPIO tables retrieved from PCDs are ignored. However, progress on those SKUs
16
* is held up because the final table passed to function similar to RC's
17
* GpioConfigureSklPch() is neither, but a zero-assigned variable. The code may be
18
* computing and dereferencing address pointers from a blob of internal data.
19
*/
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/* Pad configuration was generated automatically using intelp2m utility */
22
static
const
struct
pad_config
gpio_table
[] = {
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/* ------- GPIO Community 0 ------- */
25
26
/* ------- GPIO Group GPP_A ------- */
27
// RCIN# <= H_RCIN#
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PAD_CFG_NF
(
GPP_A0
,
NONE
, DEEP, NF1),
29
// LAD0 (ESPI_IO0) <=> LPC_AD_CPU_P0
30
PAD_CFG_NF
(
GPP_A1
, NATIVE, DEEP, NF1),
31
// LAD1 (ESPI_IO1) <=> LPC_AD_CPU_P1
32
PAD_CFG_NF
(
GPP_A2
, NATIVE, DEEP, NF1),
33
// LAD2 (ESPI_IO2) <=> LPC_AD_CPU_P2
34
PAD_CFG_NF
(
GPP_A3
, NATIVE, DEEP, NF1),
35
// LAD3 (ESPI_IO3) <=> LPC_AD_CPU_P3
36
PAD_CFG_NF
(
GPP_A4
, NATIVE, DEEP, NF1),
37
// LFRAME# (ESPI_CS#) => LPC_FRAME#_CPU
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PAD_CFG_NF
(
GPP_A5
,
NONE
, DEEP, NF1),
39
// SERIRQ <=> INT_SERIRQ
40
PAD_CFG_NF
(
GPP_A6
,
NONE
, DEEP, NF1),
41
// PIRQA# = PIRQA#
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PAD_CFG_NF
(
GPP_A7
,
NONE
, DEEP, NF1),
43
// CLKRUN# <= PM_CLKRUN#_EC
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PAD_CFG_NF
(
GPP_A8
,
NONE
, DEEP, NF1),
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// CLKOUT_LPC0 (ESPI_CLK) <= LPC_CLK_CPU_P0
46
PAD_CFG_NF
(
GPP_A9
, DN_20K, DEEP, NF1),
47
// CLKOUT_LPC1 <= LPC_CLK_CPU_P1
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PAD_CFG_NF
(
GPP_A10
, DN_20K, DEEP, NF1),
49
// GPIO (PME#) // NC
50
PAD_CFG_TERM_GPO
(
GPP_A11
, 1, DN_20K, DEEP),
51
// GPIO (SX_EXIT_HOLDOFF#/BM_BUSY#/ISH_GP6) <= GC6_FB_EN
52
PAD_CFG_GPI_TRIG_OWN
(
GPP_A12
,
NONE
, DEEP, OFF, ACPI),
53
// SUSWARN#/SUSPWRDNACK = PM_SUSACK#
54
PAD_CFG_NF
(
GPP_A13
,
NONE
, DEEP, NF1),
55
// SUS_STAT# (ESPI_RESET#) => PM_SUS_STAT#
56
PAD_CFG_NF
(
GPP_A14
,
NONE
, DEEP, NF1),
57
// SUS_ACK# = PM_SUSACK#
58
PAD_CFG_NF
(
GPP_A15
, DN_20K, DEEP, NF1),
59
// GPIO (SD_1P8_SEL) // NC
60
PAD_NC
(
GPP_A16
, DN_20K),
61
// GPIO (SD_PWR_EN#/ISH_GP7) // NC
62
PAD_NC
(
GPP_A17
, DN_20K),
63
// GPIO (ISH_GP0) => GSENSOR_INT#
64
PAD_CFG_GPI_TRIG_OWN
(
GPP_A18
,
NONE
, DEEP, OFF, ACPI),
65
// GPIO (ISH_GP1) // NC
66
PAD_NC
(
GPP_A19
, DN_20K),
67
// GPIO (ISH_GP3) // NC
68
PAD_NC
(
GPP_A21
, DN_20K),
69
// GPIO (ISH_GP4) <= GPU_EVENT#
70
PAD_CFG_GPO
(
GPP_A22
, 1, DEEP),
71
// GPIO (ISH_GP5) // NC
72
PAD_NC
(
GPP_A23
, DN_20K),
73
74
/* ------- GPIO Group GPP_B ------- */
75
// CORE_VID0 // V0.85A_VID0
76
PAD_CFG_NF
(
GPP_B0
,
NONE
, DEEP, NF1),
77
// CORE_VID1 // V0.85A_VID1
78
PAD_CFG_NF
(
GPP_B1
,
NONE
, DEEP, NF1),
79
// GPIO (CPU_GP2) <= TP_IN#
80
// TODO: APIC-routed pads don't have host owners?
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PAD_CFG_GPI_APIC_HIGH
(
GPP_B3
,
NONE
, DEEP),
82
// SRCCLKREQ0# <= PEG_CLKREQ_CPU#
83
PAD_CFG_NF
(
GPP_B5
,
NONE
, DEEP, NF1),
84
// SRCCLKREQ1# <= LAN_CLKREQ_CPU#
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PAD_CFG_NF
(
GPP_B6
,
NONE
, DEEP, NF1),
86
// SRCCLKREQ2# <= WLAN_CLKREQ_CPU#
87
PAD_CFG_NF
(
GPP_B7
,
NONE
, DEEP, NF1),
88
// SRCCLKREQ3# <= MSATA_CLKREQ_CPU#
89
PAD_CFG_NF
(
GPP_B8
,
NONE
, DEEP, NF1),
90
// SRCCLKREQ4# // SRCCLKREQ4# ("Remove TBT")
91
PAD_CFG_NF
(
GPP_B9
,
NONE
, DEEP, NF1),
92
// SRCCLKREQ5# // SRCCLKREQ5#
93
PAD_CFG_NF
(
GPP_B10
,
NONE
, DEEP, NF1),
94
// GPIO (EXT_PWR_GATE#) = EXT_PWR_GATE#
95
PAD_CFG_TERM_GPO
(
GPP_B11
, 1, DN_20K, DEEP),
96
// GPIO (SLP_S0#) // NC
97
PAD_CFG_TERM_GPO
(
GPP_B12
, 1, DN_20K, DEEP),
98
// PLTRST# => PLT_RST#
99
PAD_CFG_NF
(
GPP_B13
,
NONE
, DEEP, NF1),
100
// GPIO (SPKR) => HDA_SPKR (Strap - Top Swap Override)
101
PAD_CFG_TERM_GPO
(
GPP_B14
, 1, DN_20K, DEEP),
102
// GPIO (GSPI0_CS#) = TOUCH_DET#
103
PAD_CFG_GPO
(
GPP_B15
, 0, DEEP),
104
// GPIO (GSPI0_CLK) // NC
105
PAD_CFG_GPO
(
GPP_B16
, 0, DEEP),
106
// GPIO (GSPI0_MISO) // NC ("Remove TBT")
107
PAD_CFG_GPI_SCI
(
GPP_B17
, DN_20K, DEEP, EDGE_SINGLE, INVERT),
108
// GPIO (GSPI0_MOSI) => GPP_B18/GSPI0_MOSI (Strap - No reboot)
109
PAD_CFG_TERM_GPO
(
GPP_B18
, 1, DN_20K, DEEP),
110
// GPIO (GSPI1_CS#) => RTC_DET#
111
PAD_CFG_GPI_TRIG_OWN
(
GPP_B19
,
NONE
, DEEP, OFF, ACPI),
112
// GPIO (GSPI1_CLK) <= PSW_CLR#
113
PAD_CFG_GPI_TRIG_OWN
(
GPP_B20
, DN_20K, DEEP, OFF, ACPI),
114
// GPIO (GSPI1_MOSI) => GPP_B22/GSPI1_MOSI (Strap - Boot BIOS strap)
115
PAD_CFG_TERM_GPO
(
GPP_B22
, 1, DN_20K, DEEP),
116
// GPIO (SML1ALERT#/PCHHOT#) => GPP_B23 (Strap)
117
PAD_CFG_TERM_GPO
(
GPP_B23
, 1, DN_20K, DEEP),
118
119
/* ------- GPIO Community 1 ------- */
120
121
/* ------- GPIO Group GPP_C ------- */
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// SMBCLK <= SMB_CLK
123
PAD_CFG_NF
(
GPP_C0
,
NONE
, DEEP, NF1),
124
// SMBDATA = SMB_DATA
125
PAD_CFG_NF
(
GPP_C1
, DN_20K, DEEP, NF1),
126
// GPIO (SMBALERT#) => GPP_C2 (Strap - TLS Confidentiality)
127
PAD_CFG_TERM_GPO
(
GPP_C2
, 1, DN_20K, DEEP),
128
// GPIO (SML0CLK) // NC
129
PAD_CFG_TERM_GPO
(
GPP_C3
, 1, DN_20K, DEEP),
130
// GPIO (SML0DATA) // NC
131
PAD_CFG_TERM_GPO
(
GPP_C4
, 1, DN_20K, DEEP),
132
// GPIO (SML0ALERT#) // NC (Strap - eSPI or LPC)
133
PAD_CFG_TERM_GPO
(
GPP_C5
, 1, DN_20K, DEEP),
134
// RESERVED (SML1CLK) <=> SML1_CLK (KBC)
135
// RESERVED (SML1DATA) <=> SML1_DATA (KBC)
136
// GPIO (UART0_RXD) // NC
137
PAD_CFG_TERM_GPO
(
GPP_C8
, 1, DN_20K, DEEP),
138
// GPIO (UART0_TXD) // NC
139
PAD_CFG_TERM_GPO
(
GPP_C9
, 1, DN_20K, DEEP),
140
// GPIO (UART0_RTS#) // NC
141
PAD_CFG_TERM_GPO
(
GPP_C10
, 1, DN_20K, DEEP),
142
// GPIO (UART0_CTS#) // NC
143
PAD_CFG_TERM_GPO
(
GPP_C11
, 1, DN_20K, DEEP),
144
// GPIO (UART1_RXD/ISH_UART1_RXD) // NC
145
PAD_NC
(
GPP_C12
, DN_20K),
146
// GPIO (UART1_TXD/ISH_UART1_TXD) // NC
147
PAD_NC
(
GPP_C13
, DN_20K),
148
// GPIO (UART1_RTS#/ISH_UART1_RTS#) // NC
149
PAD_NC
(
GPP_C14
, DN_20K),
150
// GPIO (UART1_CTS#/ISH_UART1_CTS#) // NC
151
PAD_NC
(
GPP_C15
, DN_20K),
152
// I2C0_SDA <=> I2C0_DATA_CPU (Touch Panel)
153
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
154
// I2C0_SCL <=> I2C0_CLK_CPU (Touch Panel)
155
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
156
// I2C1_SDA <=> I2C1_DATA_CPU (Touch Pad)
157
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
158
// I2C1_SCL <=> I2C1_CLK_CPU (Touch Pad)
159
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
160
// UART2_RXD = LPSS_UART2_RXD
161
PAD_CFG_NF
(
GPP_C20
,
NONE
, DEEP, NF1),
162
// UART2_TXD = LPSS_UART2_TXD
163
PAD_CFG_NF
(
GPP_C21
,
NONE
, DEEP, NF1),
164
// UART2_RTS# = LPSS_UART2_RTS#
165
PAD_CFG_NF
(
GPP_C22
,
NONE
, DEEP, NF1),
166
// UART2_CTS# = LPSS_UART2_CTS#
167
PAD_CFG_NF
(
GPP_C23
,
NONE
, DEEP, NF1),
168
169
/* ------- GPIO Group GPP_D ------- */
170
// GPIO (SPI1_CS#) // NC
171
PAD_CFG_TERM_GPO
(
GPP_D0
, 1, DN_20K, DEEP),
172
// GPIO (SPI1_CLK) // NC
173
PAD_CFG_TERM_GPO
(
GPP_D1
, 1, DN_20K, DEEP),
174
// SPI1_MISO // NC
175
PAD_CFG_NF
(
GPP_D2
,
NONE
, DEEP, NF1),
176
// SPI1_MOSI // NC
177
PAD_CFG_NF
(
GPP_D3
,
NONE
, DEEP, NF1),
178
// GPIO (FLASHTRIG) // NC
179
PAD_CFG_TERM_GPO
(
GPP_D4
, 1, DN_20K, DEEP),
180
// GPIO (ISH_I2C0_SDA) // NC
181
PAD_NC
(
GPP_D5
, DN_20K),
182
// GPIO (ISH_I2C0_SCL) // NC
183
PAD_NC
(
GPP_D6
, DN_20K),
184
// GPIO (ISH_I2C1_SDA) // NC
185
PAD_NC
(
GPP_D7
, DN_20K),
186
// GPIO (ISH_I2C1_SCL) // NC
187
PAD_NC
(
GPP_D8
, DN_20K),
188
// GPIO // NC
189
PAD_CFG_GPI_TRIG_OWN
(
GPP_D9
,
NONE
, DEEP, LEVEL, ACPI),
190
// GPIO => TOUCH_S_RST#
191
PAD_CFG_GPI_TRIG_OWN
(
GPP_D10
,
NONE
, DEEP, LEVEL, ACPI),
192
// GPIO // NC
193
PAD_CFG_GPI_TRIG_OWN
(
GPP_D11
,
NONE
, DEEP, LEVEL, ACPI),
194
// GPIO // NC ("Remove TBT")
195
PAD_CFG_GPI_TRIG_OWN
(
GPP_D12
,
NONE
, DEEP, LEVEL, ACPI),
196
// GPIO (ISH_UART0_RXD/SML0BDATA/I2C4B_SDA) // NC
197
PAD_CFG_TERM_GPO
(
GPP_D13
, 1, DN_20K, DEEP),
198
// GPIO (ISH_UART0_TXD/SML0BCLK/I2C4B_SCL) // NC
199
PAD_CFG_TERM_GPO
(
GPP_D14
, 1, DN_20K, DEEP),
200
// GPIO (ISH_UART0_RTS#) // NC
201
PAD_CFG_TERM_GPO
(
GPP_D15
, 1, DN_20K, DEEP),
202
// GPIO (ISH_UART0_CTS#/SML0BALERT#) // NC
203
PAD_CFG_TERM_GPO
(
GPP_D16
, 1, DN_20K, DEEP),
204
// GPIO (DMIC_CLK1) // NC
205
PAD_NC
(
GPP_D17
, DN_20K),
206
// GPIO (DMIC_DATA1) // NC
207
PAD_NC
(
GPP_D18
, DN_20K),
208
// DMIC_CLK0 => DMIC_CLK_CON_R
209
PAD_CFG_NF
(
GPP_D19
,
NONE
, DEEP, NF1),
210
// DMIC_DATA0 => DMIC_PCH_DATA
211
PAD_CFG_NF
(
GPP_D20
,
NONE
, DEEP, NF1),
212
// SPI1_IO2 // NC
213
PAD_CFG_NF
(
GPP_D21
,
NONE
, DEEP, NF1),
214
// SPI1_IO3 // NC
215
PAD_CFG_NF
(
GPP_D22
,
NONE
, DEEP, NF1),
216
// GPIO (I2S_MCLK) // NC
217
PAD_NC
(
GPP_D23
, DN_20K),
218
219
/* ------- GPIO Group GPP_E ------- */
220
// SATAXPCIE0 (SATAGP0) = SATAGP0
221
PAD_CFG_NF
(
GPP_E0
,
NONE
, DEEP, NF1),
222
// SATAXPCIE1 (SATAGP1) // NC
223
PAD_CFG_NF
(
GPP_E1
,
NONE
, DEEP, NF1),
224
// SATAXPCIE2 (SATAGP2) = SATAGP2
225
PAD_CFG_NF
(
GPP_E2
,
NONE
, DEEP, NF1),
226
// GPIO (CPU_GP0) // NC
227
PAD_CFG_GPO
(
GPP_E3
, 1, DEEP),
228
// GPIO (DEVSLP0) // NC ("Remove DEVSLP_PCH")
229
PAD_CFG_TERM_GPO
(
GPP_E4
, 1, DN_20K, DEEP),
230
// GPIO (DEVSLP1) // NC
231
PAD_CFG_TERM_GPO
(
GPP_E5
, 1, DN_20K, DEEP),
232
// GPIO (DEVSLP2) // NC
233
PAD_CFG_TERM_GPO
(
GPP_E6
, 1, DN_20K, DEEP),
234
// GPIO (CPU_GP1) <= TOUCH_INT#
235
PAD_CFG_GPI_APIC_LOW
(
GPP_E7
,
NONE
, DEEP),
236
// SATALED# = SATA_LED#
237
PAD_CFG_NF
(
GPP_E8
,
NONE
, DEEP, NF1),
238
// USB2_OC0# = USB_OC#
239
PAD_CFG_NF
(
GPP_E9
,
NONE
, DEEP, NF1),
240
// USB2_OC1# // USB_OC#
241
PAD_CFG_NF
(
GPP_E10
,
NONE
, DEEP, NF1),
242
// USB2_OC2# // USB_OC#
243
PAD_CFG_NF
(
GPP_E11
,
NONE
, DEEP, NF1),
244
// USB2_OC3# // USB_OC#
245
PAD_CFG_NF
(
GPP_E12
,
NONE
, DEEP, NF1),
246
// DDPB_HPD0 <= DDI1_HDMI_HPD_CPU
247
PAD_CFG_NF
(
GPP_E13
,
NONE
, DEEP, NF1),
248
// DDPC_HPD1 // NC ("Remove HPD")
249
PAD_CFG_NF
(
GPP_E14
,
NONE
, DEEP, NF1),
250
// GPIO (DDPD_HPD2) <= EC_SMI#
251
// FIXME: Vendor configures as _TERM_GPO. Why?
252
PAD_CFG_GPI_SMI
(
GPP_E15
,
NONE
, DEEP, LEVEL, INVERT),
253
// GPIO (DDPE_HPD3) <= EC_SCI#
254
PAD_CFG_GPI_SCI
(
GPP_E16
,
NONE
, PLTRST, LEVEL, INVERT),
255
// EDP_HPD <= eDP_HPD_CPU
256
PAD_CFG_NF
(
GPP_E17
,
NONE
, DEEP, NF1),
257
// DDPB_CTRLCLK <=> DDI1_HDMI_CLK_CPU
258
PAD_CFG_NF
(
GPP_E18
,
NONE
, DEEP, NF1),
259
// DDPB_CTRLDATA <=> DDI1_HDMI_DATA_CPU (Strap - Display Port B Detected)
260
PAD_CFG_NF
(
GPP_E19
, DN_20K, DEEP, NF1),
261
// DDPC_CTRLCLK // NC
262
PAD_CFG_NF
(
GPP_E20
,
NONE
, DEEP, NF1),
263
// DDPC_CTRLDATA => DDPC_CDA (Strap - Display Port C Detected)
264
PAD_CFG_NF
(
GPP_E21
, DN_20K, DEEP, NF1),
265
// GPIO // NC
266
// TODO: Vendor configures as _GPIO_BIDIRECT. Why?
267
PAD_NC
(
GPP_E22
,
NONE
),
268
// GPIO => DDPD_CDA (Strap - Display Port D Detected)
269
PAD_CFG_TERM_GPO
(
GPP_E23
, 1, DN_20K, DEEP),
270
271
/* ------- GPIO Community 2 ------- */
272
273
/* -------- GPIO Group GPD -------- */
274
// GPIO (BATLOW#) = BATLOW
275
PAD_CFG_TERM_GPO
(
GPD0
, 1, DN_20K, PWROK),
276
// ACPRESENT <= AC_PRESENT
277
PAD_CFG_NF
(
GPD1
,
NONE
, PWROK, NF1),
278
// GPIO (LAN_WAKE#) = GPD2/LAN_WAKE#
279
PAD_CFG_TERM_GPO
(
GPD2
, 1, DN_20K, PWROK),
280
// PWRBTN# <= PM_PWRBTN#
281
PAD_CFG_NF
(
GPD3
, UP_20K, PWROK, NF1),
282
// SLP_S3# => PM_SLP_S3#
283
PAD_CFG_NF
(
GPD4
,
NONE
, PWROK, NF1),
284
// SLP_S4# => PM_SLP_S4#
285
PAD_CFG_NF
(
GPD5
,
NONE
, PWROK, NF1),
286
// SLP_A# // NC
287
PAD_CFG_NF
(
GPD6
, DN_20K, PWROK, NF1),
288
// GPIO (RSVD#AT15) // NC
289
PAD_CFG_TERM_GPO
(
GPD7
, 1, DN_20K, PWROK),
290
// SUSCLK => SUS_CLK_CPU
291
PAD_CFG_NF
(
GPD8
,
NONE
, PWROK, NF1),
292
// SLP_WLAN# // NC
293
PAD_CFG_NF
(
GPD9
, DN_20K, PWROK, NF1),
294
// SLP_S5# // NC
295
PAD_CFG_NF
(
GPD10
, DN_20K, PWROK, NF1),
296
// GPIO (LANPHYPC) // NC
297
PAD_CFG_TERM_GPO
(
GPD11
, 1, DN_20K, PWROK),
298
299
/* ------- GPIO Community 3 ------- */
300
301
/* ------- GPIO Group GPP_F ------- */
302
// GPIO (I2S2_SCLK) // NC
303
PAD_NC
(
GPP_F0
, DN_20K),
304
// GPIO (I2S2_SFRM) // NC
305
PAD_NC
(
GPP_F1
, DN_20K),
306
// GPIO (I2S2_TXD) // NC
307
PAD_NC
(
GPP_F2
, DN_20K),
308
// GPIO (I2S2_RXD) // NC
309
PAD_NC
(
GPP_F3
, DN_20K),
310
// GPIO (I2C2_SDA) // NC
311
PAD_NC
(
GPP_F4
, DN_20K),
312
// GPIO (I2C2_SCL) // NC
313
PAD_NC
(
GPP_F5
, DN_20K),
314
// GPIO (I2C3_SDA) // NC
315
PAD_NC
(
GPP_F6
, DN_20K),
316
// GPIO (I2C3_SCL) // NC
317
PAD_NC
(
GPP_F7
, DN_20K),
318
// GPIO (I2C4_SDA) // NC
319
PAD_CFG_TERM_GPO
(
GPP_F8
, 1, DN_20K, DEEP),
320
// GPIO (I2C4_SCL) // NC
321
PAD_CFG_TERM_GPO
(
GPP_F9
, 1, DN_20K, DEEP),
322
// GPIO (I2C5_SDA/ISH_I2C2_SDA) // NC
323
PAD_NC
(
GPP_F10
, DN_20K),
324
// GPIO (I2C5_SCL/ISH_I2C2_SCL) // NC
325
PAD_NC
(
GPP_F11
, DN_20K),
326
// GPIO (EMMC_CMD) // NC
327
PAD_NC
(
GPP_F12
, DN_20K),
328
// GPIO (EMMC_DATA0) // NC
329
PAD_NC
(
GPP_F13
, DN_20K),
330
// GPIO (EMMC_DATA1) // NC
331
PAD_NC
(
GPP_F14
, DN_20K),
332
// GPIO (EMMC_DATA2) // NC
333
PAD_NC
(
GPP_F15
, DN_20K),
334
// GPIO (EMMC_DATA3) // NC
335
PAD_NC
(
GPP_F16
, DN_20K),
336
// GPIO (EMMC_DATA4) // NC
337
PAD_NC
(
GPP_F17
, DN_20K),
338
// GPIO (EMMC_DATA5) // NC
339
PAD_NC
(
GPP_F18
, DN_20K),
340
// GPIO (EMMC_DATA6) // NC
341
PAD_NC
(
GPP_F19
, DN_20K),
342
// GPIO (EMMC_DATA7) // NC
343
PAD_NC
(
GPP_F20
, DN_20K),
344
// GPIO (EMMC_RCLK) // NC
345
PAD_NC
(
GPP_F21
, DN_20K),
346
// GPIO (EMMC_CLK) // NC
347
PAD_NC
(
GPP_F22
, DN_20K),
348
// GPIO // NC
349
PAD_CFG_GPI_APIC_HIGH
(
GPP_F23
,
NONE
, DEEP),
350
351
/* ------- GPIO Group GPP_G ------- */
352
// GPIO (SD_CMD) // NC
353
PAD_NC
(
GPP_G0
, DN_20K),
354
// GPIO (SD_DATA0) // NC
355
PAD_NC
(
GPP_G1
, DN_20K),
356
// GPIO (SD_DATA1) // NC
357
PAD_NC
(
GPP_G2
, DN_20K),
358
// GPIO (SD_DATA2) // NC
359
PAD_NC
(
GPP_G3
, DN_20K),
360
// GPIO (SD_DATA3) // NC
361
// TODO: Vendor configures as _GPO. Why?
362
PAD_NC
(
GPP_G4
,
NONE
),
363
// GPIO (SD_CD#) // NC
364
PAD_NC
(
GPP_G5
, DN_20K),
365
// GPIO (SD_CLK) // NC
366
PAD_NC
(
GPP_G6
, DN_20K),
367
// GPIO (SD_WP) // NC
368
PAD_NC
(
GPP_G7
, DN_20K),
369
};
370
371
void
mainboard_config_stage_gpios
(
void
)
372
{
373
gpio_configure_pads
(
gpio_table
,
ARRAY_SIZE
(
gpio_table
));
374
}
GPD11
#define GPD11
Definition:
gpio_soc_defs.h:392
GPP_A4
#define GPP_A4
Definition:
gpio_soc_defs.h:123
GPP_C15
#define GPP_C15
Definition:
gpio_soc_defs.h:552
GPD3
#define GPD3
Definition:
gpio_soc_defs.h:384
GPP_B6
#define GPP_B6
Definition:
gpio_soc_defs.h:59
GPP_D1
#define GPP_D1
Definition:
gpio_soc_defs.h:253
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_C2
#define GPP_C2
Definition:
gpio_soc_defs.h:539
GPP_D10
#define GPP_D10
Definition:
gpio_soc_defs.h:262
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_E3
#define GPP_E3
Definition:
gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F21
#define GPP_F21
Definition:
gpio_soc_defs.h:594
GPP_C12
#define GPP_C12
Definition:
gpio_soc_defs.h:549
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_F16
#define GPP_F16
Definition:
gpio_soc_defs.h:589
GPP_E0
#define GPP_E0
Definition:
gpio_soc_defs.h:628
GPP_F6
#define GPP_F6
Definition:
gpio_soc_defs.h:579
GPP_D14
#define GPP_D14
Definition:
gpio_soc_defs.h:266
GPP_B1
#define GPP_B1
Definition:
gpio_soc_defs.h:54
GPP_F20
#define GPP_F20
Definition:
gpio_soc_defs.h:593
GPP_F23
#define GPP_F23
Definition:
gpio_soc_defs.h:596
GPP_C5
#define GPP_C5
Definition:
gpio_soc_defs.h:542
GPP_A14
#define GPP_A14
Definition:
gpio_soc_defs.h:133
GPP_B12
#define GPP_B12
Definition:
gpio_soc_defs.h:65
GPP_D12
#define GPP_D12
Definition:
gpio_soc_defs.h:264
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_A5
#define GPP_A5
Definition:
gpio_soc_defs.h:124
GPP_D7
#define GPP_D7
Definition:
gpio_soc_defs.h:259
GPP_B13
#define GPP_B13
Definition:
gpio_soc_defs.h:66
GPP_E6
#define GPP_E6
Definition:
gpio_soc_defs.h:634
GPP_F0
#define GPP_F0
Definition:
gpio_soc_defs.h:573
GPP_D6
#define GPP_D6
Definition:
gpio_soc_defs.h:258
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_D2
#define GPP_D2
Definition:
gpio_soc_defs.h:254
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPD0
#define GPD0
Definition:
gpio_soc_defs.h:380
GPP_D9
#define GPP_D9
Definition:
gpio_soc_defs.h:261
GPP_F5
#define GPP_F5
Definition:
gpio_soc_defs.h:578
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_E13
#define GPP_E13
Definition:
gpio_soc_defs.h:641
GPP_A2
#define GPP_A2
Definition:
gpio_soc_defs.h:121
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_D11
#define GPP_D11
Definition:
gpio_soc_defs.h:263
GPP_A6
#define GPP_A6
Definition:
gpio_soc_defs.h:125
GPP_C11
#define GPP_C11
Definition:
gpio_soc_defs.h:548
GPP_D5
#define GPP_D5
Definition:
gpio_soc_defs.h:257
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_F9
#define GPP_F9
Definition:
gpio_soc_defs.h:582
GPP_C13
#define GPP_C13
Definition:
gpio_soc_defs.h:550
GPP_E14
#define GPP_E14
Definition:
gpio_soc_defs.h:642
GPP_E23
#define GPP_E23
Definition:
gpio_soc_defs.h:651
GPP_E9
#define GPP_E9
Definition:
gpio_soc_defs.h:637
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_E8
#define GPP_E8
Definition:
gpio_soc_defs.h:636
GPP_A7
#define GPP_A7
Definition:
gpio_soc_defs.h:126
GPP_E5
#define GPP_E5
Definition:
gpio_soc_defs.h:633
GPP_A0
#define GPP_A0
Definition:
gpio_soc_defs.h:119
GPD7
#define GPD7
Definition:
gpio_soc_defs.h:388
GPP_B8
#define GPP_B8
Definition:
gpio_soc_defs.h:61
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_B20
#define GPP_B20
Definition:
gpio_soc_defs.h:73
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_F1
#define GPP_F1
Definition:
gpio_soc_defs.h:574
GPP_F17
#define GPP_F17
Definition:
gpio_soc_defs.h:590
GPP_A12
#define GPP_A12
Definition:
gpio_soc_defs.h:131
GPP_F15
#define GPP_F15
Definition:
gpio_soc_defs.h:588
GPP_D4
#define GPP_D4
Definition:
gpio_soc_defs.h:256
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPD2
#define GPD2
Definition:
gpio_soc_defs.h:383
GPP_F10
#define GPP_F10
Definition:
gpio_soc_defs.h:583
GPP_A3
#define GPP_A3
Definition:
gpio_soc_defs.h:122
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_F7
#define GPP_F7
Definition:
gpio_soc_defs.h:580
GPD1
#define GPD1
Definition:
gpio_soc_defs.h:382
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_D18
#define GPP_D18
Definition:
gpio_soc_defs.h:270
GPP_B19
#define GPP_B19
Definition:
gpio_soc_defs.h:72
GPP_E17
#define GPP_E17
Definition:
gpio_soc_defs.h:645
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_E19
#define GPP_E19
Definition:
gpio_soc_defs.h:647
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPD10
#define GPD10
Definition:
gpio_soc_defs.h:391
GPP_E18
#define GPP_E18
Definition:
gpio_soc_defs.h:646
GPP_F14
#define GPP_F14
Definition:
gpio_soc_defs.h:587
GPP_F4
#define GPP_F4
Definition:
gpio_soc_defs.h:577
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_D0
#define GPP_D0
Definition:
gpio_soc_defs.h:252
GPP_A1
#define GPP_A1
Definition:
gpio_soc_defs.h:120
GPP_B14
#define GPP_B14
Definition:
gpio_soc_defs.h:67
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_D13
#define GPP_D13
Definition:
gpio_soc_defs.h:265
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_B5
#define GPP_B5
Definition:
gpio_soc_defs.h:58
GPP_B0
#define GPP_B0
Definition:
gpio_soc_defs.h:53
GPP_A11
#define GPP_A11
Definition:
gpio_soc_defs.h:130
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_E20
#define GPP_E20
Definition:
gpio_soc_defs.h:648
GPP_A15
#define GPP_A15
Definition:
gpio_soc_defs.h:134
GPP_A9
#define GPP_A9
Definition:
gpio_soc_defs.h:128
GPP_E10
#define GPP_E10
Definition:
gpio_soc_defs.h:638
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPD8
#define GPD8
Definition:
gpio_soc_defs.h:389
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_A21
#define GPP_A21
Definition:
gpio_soc_defs.h:140
GPP_B23
#define GPP_B23
Definition:
gpio_soc_defs.h:76
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_E16
#define GPP_E16
Definition:
gpio_soc_defs.h:644
GPP_D19
#define GPP_D19
Definition:
gpio_soc_defs.h:271
GPP_C1
#define GPP_C1
Definition:
gpio_soc_defs.h:538
GPP_F2
#define GPP_F2
Definition:
gpio_soc_defs.h:575
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPD6
#define GPD6
Definition:
gpio_soc_defs.h:387
GPP_F18
#define GPP_F18
Definition:
gpio_soc_defs.h:591
GPP_B3
#define GPP_B3
Definition:
gpio_soc_defs.h:56
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
GPP_D15
#define GPP_D15
Definition:
gpio_soc_defs.h:267
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPD4
#define GPD4
Definition:
gpio_soc_defs.h:385
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_F3
#define GPP_F3
Definition:
gpio_soc_defs.h:576
GPP_E22
#define GPP_E22
Definition:
gpio_soc_defs.h:650
GPP_E21
#define GPP_E21
Definition:
gpio_soc_defs.h:649
GPP_C3
#define GPP_C3
Definition:
gpio_soc_defs.h:540
GPP_E12
#define GPP_E12
Definition:
gpio_soc_defs.h:640
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_E4
#define GPP_E4
Definition:
gpio_soc_defs.h:632
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPD5
#define GPD5
Definition:
gpio_soc_defs.h:386
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_B7
#define GPP_B7
Definition:
gpio_soc_defs.h:60
GPP_D3
#define GPP_D3
Definition:
gpio_soc_defs.h:255
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
GPP_D23
#define GPP_D23
Definition:
gpio_soc_defs.h:133
GPP_G1
#define GPP_G1
Definition:
gpio_soc_defs.h:89
GPP_G7
#define GPP_G7
Definition:
gpio_soc_defs.h:95
GPP_D22
#define GPP_D22
Definition:
gpio_soc_defs.h:132
GPP_G4
#define GPP_G4
Definition:
gpio_soc_defs.h:92
GPP_G2
#define GPP_G2
Definition:
gpio_soc_defs.h:90
GPP_D21
#define GPP_D21
Definition:
gpio_soc_defs.h:131
GPP_G6
#define GPP_G6
Definition:
gpio_soc_defs.h:94
GPP_G0
#define GPP_G0
Definition:
gpio_soc_defs.h:88
GPP_D20
#define GPP_D20
Definition:
gpio_soc_defs.h:130
GPP_G3
#define GPP_G3
Definition:
gpio_soc_defs.h:91
GPP_G5
#define GPP_G5
Definition:
gpio_soc_defs.h:93
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.c:22
mainboard_config_stage_gpios
void mainboard_config_stage_gpios(void)
Definition:
gpio.c:371
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
gpio_configure_pads
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition:
gpio.c:307
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_GPI_SMI
#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:412
PAD_CFG_GPI_TRIG_OWN
#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own)
Definition:
gpio_defs.h:311
PAD_CFG_TERM_GPO
#define PAD_CFG_TERM_GPO(pad, val, pull, rst)
Definition:
gpio_defs.h:262
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_APIC_HIGH
#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst)
Definition:
gpio_defs.h:405
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_SCI
#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:432
PAD_CFG_GPI_APIC_LOW
#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst)
Definition:
gpio_defs.h:402
gpio.h
pad_config
Definition:
gpio.h:75
src
mainboard
acer
aspire_vn7_572g
gpio.c
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