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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <types.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
#include <cpu/intel/model_2065x/model_2065x.h>
#include <southbridge/intel/common/finalize.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/ibexpeak/me.h>
#include "pch.h"
#include <northbridge/intel/ironlake/ironlake.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmutil.h>
Go to the source code of this file.
Macros | |
#define | IOTRAP(x) (trap_sts & (1 << x)) |
Functions | |
static void | southbridge_gate_memory_reset_real (int offset, u16 use, u16 io, u16 lvl) |
void | southbridge_gate_memory_reset (void) |
void | southbridge_smi_monitor (void) |
void | southbridge_finalize_all (void) |
Definition at line 129 of file smihandler.c.
References intel_ironlake_finalize_smm(), intel_model_2065x_finalize_smm(), and intel_pch_finalize_smm().
Definition at line 55 of file smihandler.c.
References GP_IO_SEL, GP_IO_SEL2, GP_LVL, GP_LVL2, GPIO_USE_SEL, GPIO_USE_SEL2, GPIOBASE, PCI_DEV, pci_read_config16(), and southbridge_gate_memory_reset_real().
Definition at line 24 of file smihandler.c.
References inl(), offset, and outl().
Referenced by southbridge_gate_memory_reset().
Definition at line 75 of file smihandler.c.
References BIOS_DEBUG, IOTRAP, mask, printk, and RCBA32.